74LVC2G241GM-G NXP Semiconductors, 74LVC2G241GM-G Datasheet

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74LVC2G241GM-G

Manufacturer Part Number
74LVC2G241GM-G
Description
Buffers & Line Drivers 3.3V DUAL BUF/LDRVR 5V I/O 3S
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC2G241GM-G

Product Category
Buffers & Line Drivers
Rohs
yes
Number Of Input Lines
2
Number Of Output Lines
2
Polarity
Non-Inverting
Supply Voltage - Max
5.5 V
Supply Voltage - Min
1.65 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOT-902-8
High Level Output Current
- 32 mA
Logic Family
LVC
Logic Type
CMOS
Low Level Output Current
32 mA
Minimum Operating Temperature
- 40 C
Number Of Channels Per Chip
2
Output Type
3-State
Propagation Delay Time
2.8 ns at 2.7 V
Factory Pack Quantity
4000
Part # Aliases
74LVC2G241GM,125
1. General description
2. Features and benefits
The 74LVC2G241 is a dual non-inverting buffer/line driver with 3-state outputs. The
3-state outputs are controlled by the output enable inputs 1OE and 2OE:
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the
74LVC2G241 as a translator in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
74LVC2G241
Dual buffer/line driver; 3-state
Rev. 12 — 22 June 2012
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
ESD protection:
±24 mA output drive (V
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C
A HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state.
A LOW level at pin 2OE causes output 2Y to assume a high-impedance OFF-state.
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CC
= 3.0 V)
Product data sheet
OFF
. The I
OFF

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74LVC2G241GM-G Summary of contents

Page 1

Dual buffer/line driver; 3-state Rev. 12 — 22 June 2012 1. General description The 74LVC2G241 is a dual non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE: • A ...

Page 2

... Marking Table 2. Marking codes Type number 74LVC2G241DP 74LVC2G241DC 74LVC2G241GT 74LVC2G241GF 74LVC2G241GD 74LVC2G241GM 74LVC2G241GN 74LVC2G241GS [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 74LVC2G241 Product data sheet Description TSSOP8 plastic thin shrink small outline package; 8 leads; ...

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... NXP Semiconductors 5. Functional diagram 1OE 1A 2OE 2A 001aah844 Fig 1. Logic symbol 6. Pinning information 6.1 Pinning 74LVC2G241 1OE GND 001aab569 Fig 3. Pin configuration SOT505-2 and SOT765-1 74LVC2G241 Product data sheet 1Y 2Y Fig 2OE Fig 4. All information provided in this document is subject to legal disclaimers. ...

Page 4

... NXP Semiconductors 74LVC2G241 1OE GND 4 Transparent top view Fig 5. Pin configuration SOT996-2 6.2 Pin description Table 3. Pin description Symbol Pin SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 1OE 1 1A GND 4 1Y 2OE Functional description [1] Table 4. ...

Page 5

... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I output current ...

Page 6

... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = −40 °C to +85 °C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V LOW-level output voltage OL V HIGH-level output voltage input leakage current ...

Page 7

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = −40 °C to +125 °C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V LOW-level output voltage OL V HIGH-level output voltage input leakage current I I OFF-state output current ...

Page 8

... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t propagation delay nA to nY; see enable time 1OE to 1Y; see 2OE to 2Y; see disable time 1OE to 1Y ...

Page 9

... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions C power dissipation per buffer capacitance output enabled output disabled [1] Typical values are measured at nominal V [ the same as t and PLH ...

Page 10

... NXP Semiconductors 1OE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in Logic levels: V and Fig 8. Enable and disable times for input 1OE 2OE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH ...

Page 11

... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Test voltage for switching times. EXT Fig 10. Test circuit for measuring switching times Table 10 ...

Page 12

... NXP Semiconductors 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.00 0.75 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...

Page 13

... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. 8× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

Page 15

... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1. 0.5 mm terminal 1 index area (2) (4× terminal 1 index area Dimensions (1) Unit max 0.5 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version ...

Page 16

... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 15. Package outline SOT996-2 (XSON8U) 74LVC2G241 Product data sheet ...

Page 17

... NXP Semiconductors XQFN8: plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1 terminal 1 index area terminal 1 index area L 1 Dimensions (1) Unit max 0.5 0.05 0.25 1.65 mm nom 0.20 1.60 min 0.00 0.15 1.55 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline ...

Page 18

... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.25 mm nom 0.15 1.20 min 0.12 1.15 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version IEC SOT1116 Fig 17. Package outline SOT1116 (XSON8) ...

Page 19

... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version IEC SOT1203 Fig 18. Package outline SOT1203 (XSON8) ...

Page 20

... Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date 74LVC2G241 v.12 20120622 • Modifications: For type number 74LVC2G241GM the SOT code has changed to SOT902-2. 74LVC2G241 v.11 20111129 • Modifications: Legal pages updated. 74LVC2G241 v.10 20100806 74LVC2G241 v.9 20080610 74LVC2G241 v.8 20080312 74LVC2G241 v.7 20071005 74LVC2G241 v ...

Page 21

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 22

... Product data sheet NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 23

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Package outline ...

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