FM25L256-DGTR Cypress Semiconductor, FM25L256-DGTR Datasheet - Page 5

• Manufacturer Part Number: FM25L256-DGTR
• Description: F-RAM 256K (32Kx8) 2.7V
• Manufacturer: Cypress Semiconductor

Specifications of FM25L256-DGTR

• Product Category: F-RAM
• Rohs: yes
• Memory Size: 256 KB
• Organization: 32 K x 8
• Interface: SPI
• Operating Supply Voltage: 2.7 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: DFN-8
• Factory Pack Quantity: 3000

Power Up to First Access
The FM25L256 is not accessible for a period of time
(10 ms) after power up. Users must comply with the
timing parameter t
from V
Data Transfer
All data transfers to and from the FM25L256 occur in
8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25L256. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the status
register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
Table 1. Op-Code Commands
Rev. 2.4 (obsolete)
Feb. 2009
Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
DD
(min) to the first /CS low.
Description
Set Write Enable Latch
Write Disable
Read Status Register
Write Status Register
Read Memory Data
Write Memory Data
SCK
SO
CS
SI
PU
, which is the minimum time
0
0
0
1
Op-Code
0000 0110b
0000 0100b
0000 0101b
0000 0001b
0000 0011b
0000 0010b
Figure 5. WREN Bus Configuration
0
2
0
3
Hi-Z
0
4
WREN - Set Write Enable Latch
The FM25L256 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the status
register and writing the memory.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that
Attempting to write the WEL bit in the status
register has no effect on the state of this bit.
Completing any write operation will automatically
clear the write-enable latch and prevent further
writes without another WREN command. Figure 5
below
configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
6 illustrates the WRDI command bus configuration.
1
5
illustrates
1
6
7
0
the
FM25L256 Extended Temp.
WREN
writes are permitted.
command
Page 5 of 14
bus