24C01C-I/SN Microchip Technology, 24C01C-I/SN Datasheet - Page 11

• Manufacturer Part Number: 24C01C-I/SN
• Description: IC EEPROM 1KBIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24C01C-I/SN

• Memory Size: 1K (128 x 8)
• Package / Case: 8-SOIC (3.9mm Width)
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Organization: 128 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 1 ms
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 4.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

8.0
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
The 24C01C contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n, the next current address read
operation would access data from address n + 1. Upon
receipt of the slave address with the R/W bit set to one,
the 24C01C issues an acknowledge and transmits the
eight-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
24C01C discontinues transmission (Figure 8-1).
FIGURE 8-1:
FIGURE 8-2:
FIGURE 8-3:
© 2008 Microchip Technology Inc.
Bus Activity
Master
SDA Line
Bus Activity
Bus Activity
Master
SDA Line
Bus Activity
READ OPERATION
Current Address Read
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
S
CURRENT ADDRESS
READ
RANDOM READ
SEQUENTIAL READ
Control
Byte
Control
Byte
S
T
A
R
T
S
A
C
K
A
C
K
Control
Byte
Data n
Data
A
C
K
N
O
C
Address (n)
A
C
K
A
K
S
T
O
P
P
Word
Data n + 1
8.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C01C as part of a write operation.
After the word address is sent, the master generates a
Start condition following the acknowledge. This
terminates the write operation, but not before the
internal Address Pointer is set. Then the master issues
the control byte again but with the R/W bit set to a one.
The 24C01C will then issue an acknowledge and trans-
mits the eight bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition and the 24C01C discontinues transmission
(Figure 8-2). After this command, the internal address
counter will point to the address location following the
one that was just read.
8.3
Sequential reads are initiated in the same way as a
random read except that after the 24C01C transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24C01C to transmit the next sequentially
addressed 8-bit word (Figure 8-3).
To provide sequential reads the 24C01C contains an
internal Address Pointer which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation. The internal Address
Pointer will automatically roll over from address 7F to
address 00.
A
C
K
S
T
A
R
T
S
A
C
K
Control
Random Read
Sequential Read
Data n + 2
Byte
A
C
K
A
C
K
Data (n)
Data n + X
24C01C
DS21201J-page 11
O
N
A
C
K
S
T
O
P
P
N
O
A
C
K
S
T
O
P
P