24C01C-I/SN Microchip Technology, 24C01C-I/SN Datasheet - Page 6

• Manufacturer Part Number: 24C01C-I/SN
• Description: IC EEPROM 1KBIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24C01C-I/SN

• Memory Size: 1K (128 x 8)
• Package / Case: 8-SOIC (3.9mm Width)
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Organization: 128 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 1 ms
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 4.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

24C01C
3.0
The 24C01C supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device that generates the Serial Clock
(SCL), controls the bus access, and generates the Start
and Stop conditions, while the 24C01C works as slave.
Both master and slave can operate as transmitter or
receiver, but the master device determines which mode
is activated.
4.0
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
• During data transfer, the data line must remain
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Both data and clock lines remain high.
4.2
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
DS21201J-page 6
is not busy.
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
FUNCTIONAL DESCRIPTION
BUS CHARACTERISTICS
Bus Not Busy (A)
Start Data Transfer (B)
Stop Data Transfer (C)
4.4
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first-in first-
out fashion.
4.5
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse, which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line high to enable the
master to generate the Stop condition (Figure 4-2)
Note:
Data Valid (D)
Acknowledge
The 24C01C does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress.
© 2008 Microchip Technology Inc.