L6564TD STMicroelectronics, L6564TD Datasheet - Page 23

• Manufacturer Part Number: L6564TD
• Description: Power Factor Correction ICs 10-Pin Trans Mode PFC Bi 6mA 0.75W
• Manufacturer: STMicroelectronics

Specifications of L6564TD

• Rohs: yes
• Maximum Power Dissipation: 0.75 W
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-10
• Minimum Operating Temperature: - 40 C

L6564T
Figure 31. THD optimization: standard TM PFC controller (left side) and L6564T (right side)
6.5
Essentially, the circuit artificially increases the ON-time of the power switch with a positive
offset added to the output of the multiplier in the proximity of the line voltage zero-crossings.
This offset is reduced as the instantaneous line voltage increases, so that it becomes
negligible as the line voltage moves toward the top of the sinusoid. Furthermore, the offset is
modulated by the voltage on the VFF pin (see
line, where energy transfer at zero crossings is typically quite good, and a larger offset at
high line where the energy transfer gets worse.
The effect of the circuit is shown in
PFC controller are compared to those of this chip.
To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor
after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large
capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself -
even with an ideal energy transfer by the PFC pre-regulator - therefore reducing the
effectiveness of the optimizer circuit.
Inductor saturation detection
The boost inductor's hard saturation may be a fatal event for a PFC pre-regulator: the
current up-slope becomes so large (50-100 times steeper, see
current sense propagation delay the current may reach abnormally high values. The voltage
drop caused by this abnormal current on the sense resistor reduces the gate-to-source
voltage, so that the MOSFET may work in the active region and dissipate a huge amount of
power, which leads to a catastrophic failure after few switching cycles.
Input current
Imains
Rectified mains voltage
Input current
MOSFET's drain voltage
Vdrain
Doc ID 022671 Rev 1
Figure 31
Input current
Imains
, where the key waveforms of a standard TM
Section 6.3
Rectified mains voltage
) so as to have little offset at low
MOSFET's drain voltage
Input current
Figure 32
Application information
Vdrain
) that during the
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