CY62136EV30LL-45ZSXI Cypress Semiconductor Corp, CY62136EV30LL-45ZSXI Datasheet - Page 5

• Manufacturer Part Number: CY62136EV30LL-45ZSXI
• Description: IC SRAM 2MBIT 45NS 44TSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62136EV30LL-45ZSXI

• Memory Size: 2M (128K x 16)
• Package / Case: 44-TSOP II
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 45 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.2 V
• Maximum Operating Current: 20 mA
• Organization: 128 K x 16
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 2.5 V or 3.3 V
• Memory Configuration: 128K X 16
• Supply Voltage Range: 2.2V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2068; CY62136EV30LL-45ZSXI

Thermal Resistance
Data Retention Characteristics
(Over the Operating Range)
Data Retention Waveform
Document #: 38-05569 Rev. *D
V
I
t
t
Notes
Parameter
CCDR
CDR
R
11. Tested initially and after any design or process changes that may affect these parameters.
12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
13. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
14. Full device operation requires linear V
15. BHE.BLE is the AND of both BHE and BLE. The chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
DR
[14]
Parameter
[11]


[13]
JA
JC
V
CE
CC
[11]
Parameters
OUTPUT
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
INCLUDING
R
V
R1
R2
V
JIG AND
TH
TH
V
Data retention current
Chip deselect to data
retention time
Operation recovery time
SCOPE
CC
CC
Description
for data retention
30 pF
Description
R1
CC
ramp from V
[15]
V
R2
Figure 1. AC Test Loads and Waveforms
CC(min)
t
CDR
Still air, soldered on a 3 × 4.5 inch, two-layer printed
circuit board
DR
V
CE > V
V
Rise Time = 1 V/ns
CC
IN
to V
2.50 V
16667
15385
8000
1.20
> V
= 1.0 V
CC(min.)
V
CC
CC
CC
GND
Equivalent to: THÉVENIN EQUIVALENT
– 0.2 V,
– 0.2 V or V
> 100 s or stable at V
DATA RETENTION MODE
Conditions
Test Conditions
10%
OUTPUT
V
DR
IN
> 1.0 V
< 0.2 V
ALL INPUT PULSES
90%
CC(min.)
3.0 V
1103
1554
1.75
645
SB1
> 100 s.
/ I
SB2
/ I
R
CCDR
TH
90%
specification. Other inputs can be left floating
Min
CC
1.0
45
10%
–
0
V
CY62136EV30 MoBL
= V
Fall Time = 1 V/ns
CC(min)
Package
V
t
CC(typ.)
VFBGA
R
TH
75
10
Typ
, T
0.8
A
–
–
= 25 °C
[12]
Unit



V
Package
TSOP II
77
13
Max
–
3
–
–
Page 5 of 15
C / W
C / W
Unit
Unit
A
ns
ns
V
®
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