CY62136EV30LL-45ZSXI Cypress Semiconductor Corp, CY62136EV30LL-45ZSXI Datasheet - Page 6

• Manufacturer Part Number: CY62136EV30LL-45ZSXI
• Description: IC SRAM 2MBIT 45NS 44TSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62136EV30LL-45ZSXI

• Memory Size: 2M (128K x 16)
• Package / Case: 44-TSOP II
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 45 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.2 V
• Maximum Operating Current: 20 mA
• Organization: 128 K x 16
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 2.5 V or 3.3 V
• Memory Configuration: 128K X 16
• Supply Voltage Range: 2.2V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2068; CY62136EV30LL-45ZSXI

Switching Characteristics
Document #: 38-05569 Rev. *D
Notes
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
BW
SD
HD
HZWE
LZWE
16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
17. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Refer application note
18. At any given temperature and voltage condition, t
19. t
20. The internal write time of the memory is defined by the overlap of WE, CE = V
pulse levels of 0 to V
given device.
these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the
write.
HZOE
Parameter
, t
HZCE
[20]
, t
HZBE
[16, 17]
, and t
CC(typ.)
HZWE
, and output loading of the specified I
transitions are measured when the outputs enter a high impedence state.
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to LOW Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to power-up
CE HIGH to power-down
BLE/BHE LOW to data valid
BLE/BHE LOW to Low Z
BLE/BHE HIGH to HIGH Z
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
BLE/BHE LOW to write end
Data setup to write end
Data hold from write end
WE LOW to High Z
WE HIGH to Low Z
Over the Operating Range
HZCE
is less than t
[18]
[18, 19]
[18, 19]
[18]
[18]
[18, 19]
Description
[18]
OL
[18, 19]
LZCE
/I
OH
, t
as shown in
HZBE
IL
is less than t
, BHE and BLE = V
AC Test Loads and
LZBE
, t
HZOE
IL
. All signals must be ACTIVE to initiate a write and any of
is less than t
Waveforms.
Min
45
10
10
45
35
35
35
35
25
10
–
–
–
5
–
–
0
–
–
5
–
0
0
0
–
LZOE
CY62136EV30 MoBL
45 ns
, and t
HZWE
AN13842
Max
is less than t
45
45
22
18
18
45
22
18
18
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
for more information.
CC(typ)
LZWE
Page 6 of 15
Unit
/2, input
ns
ns
ns
ns
ns
for any
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
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