CY7C1019D-10VXI Cypress Semiconductor Corp, CY7C1019D-10VXI Datasheet - Page 5

• Manufacturer Part Number: CY7C1019D-10VXI
• Description: IC SRAM 1MBIT 10NS 32SOJ
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C1019D-10VXI

• Memory Size: 1M (128K x 8)
• Package / Case: 32-SOJ
• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 10 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 80 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 5 V
• Memory Configuration: 128K X 8
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: SOJ
• No. Of Pins: 32
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Density: 1Mb
• Access Time (max): 10ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 17b
• Package Type: SOJ
• Operating Temp Range: -40C to 85C
• Supply Current: 80mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 128K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1964-5; CY7C1019D-10VXI

Switching Characteristics
Notes
Document #: 38-05464 Rev. *F
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
6. t
7. t
8. At any given temperature and voltage condition, t
9. This parameter is guaranteed by design and is not tested.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of
11. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
I
high impedance state.
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
[9]
[9]
Parameter
OL
POWER
HZOE
/I
[6]
OH
, t
HZCE
and 30-pF load capacitance.
gives the minimum amount of time that the power supply should be at typical V
, and t
[10, 11]
HZWE
V
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
are specified with a load capacitance of 5 pF as in (c) of
CC
(typical) to the first access
(Over the Operating Range)
[8]
[7, 8]
[8]
[7, 8]
[7, 8]
Description
HZCE
is less than t
LZCE
, t
HZOE
“AC Test Loads and Waveforms
[5]
is less than t
CC
LZOE
values until the first memory access can be performed.
, and t
HZWE
HZWE
and t
[4]
Min
100
SD
is less than t
10
10
” on page
3
0
3
0
7
7
0
0
7
6
0
3
.
–10 (Industrial)
4. Transition is measured when the outputs enter a
LZWE
for any given device.
Max
10
10
10
5
5
5
5
CY7C1019D
Page 5 of 13
Unit
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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