IDT7025L15PFG IDT, Integrated Device Technology Inc, IDT7025L15PFG Datasheet
IDT7025L15PFG
Specifications of IDT7025L15PFG
800-1364
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IDT7025L15PFG Summary of contents
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... Features True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Military: 20/25/35/55/70ns (max.) – Industrial: 55ns (max.) – Commercial: 15/17/20/25/35/55ns (max.) Low-power operation – IDT7025S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7025L Active: 750mW (typ.) Standby: 1mW (typ ...
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... This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by Chip Enable (CE) permits the on-chip circuitry of each Pin Configurations ...
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IDT7025S/L High-Speed Dual-Port Static RAM Pin Configurations (1,2, I/O I I/O I/O 10L I/O I/O 11L I/O I/O 13L 12L 72 ...
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IDT7025S/L High-Speed Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Pin Names Left Port Right Port R/W R 12L ...
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IDT7025S/L High-Speed Dual-Port Static RAM Truth Table I: Non-Contention Read/Write Control (1) Inputs R ...
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IDT7025S/L High-Speed Dual-Port Static RAM Absolute Maximum Ratings Symbol Rating Commercial & Industrial (2) V Terminal Voltage -0.5 to +7.0 TERM with Respect to GND T Temperature -55 to +125 BIAS Under Bias T Storage -65 to ...
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IDT7025S/L High-Speed Dual-Port Static RAM DC Electrical Characteristics Over the 0perating Temperature and Supply Voltage Range Symbol Parameter Test Condition Dynamic Operating CC , Outputs Disabled IL Current SEM = V IH (Both ...
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IDT7025S/L High-Speed Dual-Port Static RAM Data Retention Characteristics Over All Temperature Ranges (L Version Only) Symbol Parameter V V for Data Retention Data Retention Current CCDR (3) t Chip Dese lect to Data Retention ...
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IDT7025S/L High-Speed Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA t (3) Chip Enable Access Time ACE ...
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IDT7025S/L High-Speed Dual-Port Static RAM Waveform of Read Cycles ADDR CE OE UB, LB R/W DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends ...
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IDT7025S/L High-Speed Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Symbol Parameter WRITE CYCLE t Write Cycle Time WC (3) t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW ...
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... R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the IH To access Semaphore 6.42 12 (1,5, for memory array writing cycle allow the I/O drivers to turn off and data & LB and SEM = must be met = , . 2683 drw 09 (1,5) 2683 drw 10 ...
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IDT7025S/L High-Speed Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS t AW SEM DATA R/W OE Write Cycle NOTE ...
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IDT7025S/L High-Speed Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range Symbol Parameter BUSY TIMING (M BUSY Access Time from Address Match t BAA BUSY Disable Time from Address ...
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IDT7025S/L High-Speed Dual-Port Static RAM Timing Waveform of Write Port-to-Port Read and BUSY ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier ...
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IDT7025S/L High-Speed Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M/S ...
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IDT7025S/L High-Speed Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" ( "A" R/W "A" INT "B" ADDR "B" "B" OE "B" INT "B" NOTES: 1. All timing is the same ...
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... IH the memory location 1FFF user-defined, since addressable SRAM location. If the interrupt function is not used, address locations 1FFE and 1FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table I for the interrupt operation. 6.42 18 and BUSY outputs cannot be LOW simultaneously ...
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IDT7025S/L High-Speed Dual-Port Static RAM Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to ...
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... Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 4K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0 ...
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... Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “ ...
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IDT7025S/L High-Speed Dual-Port Static RAM Ordering Information XXXXX A 999 A Device Power Speed Package Type NOTE: 1. Industrial range is available on selected PLCC packages in standard power. For other speeds, packages and powers contact your ...