CY7C09369V-12AC Cypress Semiconductor Corp, CY7C09369V-12AC Datasheet - Page 2

• Manufacturer Part Number: CY7C09369V-12AC
• Description: IC SRAM 288KBIT 12NS 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09369V-12AC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 288K (16K x 18)
• Speed: 12ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1448

Functional Description
The CY7C09269V/79V/89V and CY7C09369V/79V/89V are
high-speed 3.3V synchronous CMOS 16K, 32K, and 64K x
16/18 dual-port static RAMs. Two ports are provided, permit-
ting independent, simultaneous access for reads and writes to
any location in memory.
data lines allow for minimal set-up and hold times. In pipelined
output mode, data is registered for decreased cycle time.
Clock to data valid t
mode can also be used to bypass the pipelined output register
to eliminate access latency. In flow-through mode data will be
available t
device. Pipelined output or flow-through mode is selected via
the FT/Pipe pin.
Each port contains a burst counter on the input address regis-
ter. The internal write pulse width is independent of the LOW
to HIGH transition of the clock signal. The internal write pulse
is self-timed to allow the shortest possible cycle times.
Pin Configurations
Notes:
Document #: 38-06056 Rev. **
6.
7.
8.
9.
When writing simultaneously to the same location, the final value cannot be guaranteed.
This pin is NC for CY7C09269V.
This pin is NC for CY7C09269V and CY7C09279V.
For CY7C09269V and CY7C09279V, pin #18 connected to V
compatible to an IDT 5V x16 flow-through device.
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CD1
CNTRSTL
FT/PIPEL
[ 7 ]
[ 8 ]
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
CE0L
CE1L
R/WL
= 18 ns after the address is clocked into the
A10L
A11L
A12L
A13L
A14L
A15L
GND
VCC
OEL
UBL
A9L
LBL
NC
NC
CD2
= 6.5 ns
[6]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Registers on control, address, and
100
26
99
27
[1, 2]
98
28
(pipelined). Flow-through
97
29
96
30
95
31
CY7C09289V (64K x 16)
CY7C09279V (32K x 16)
CY7C09269V (16K x 16)
94
32
93
33
100-Pin TQFP (Top View)
92 91 90
34 35 36
CC
is pin compatible to an IDT 5V x16 pipelined device; connecting pin #18 and #58 to GND is pin
89
37
88
38
87 86
39 40
A HIGH on CE
down the internal circuitry to reduce the static power consump-
tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelined mode, one cycle is required with CE
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW to HIGH tran-
sition of that port’s clock signal. This will read/write one word
from/into each successive address location until CNTEN is
deasserted. The counter can address the entire memory array
and will loop back to the start. Counter Reset (CNTRST) is
used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
85
41
84
42
83 82 81
43 44 45
0
or LOW on CE
80
46
79
47
CY7C09269V/79V/89V
CY7C09369V/79V/89V
78 77
48 49
1
76
50
for one clock cycle will power
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A9R
A10R
A11R
A12R
A13R
A14R
A15R
NC
NC
LBR
UBR
CE0R
CE1R
CNTRSTR
GND
R/WR
OER
FT/PIPER
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
0
LOW and CE
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