CY7C09369V-12AC Cypress Semiconductor Corp, CY7C09369V-12AC Datasheet - Page 4

• Manufacturer Part Number: CY7C09369V-12AC
• Description: IC SRAM 288KBIT 12NS 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09369V-12AC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 288K (16K x 18)
• Speed: 12ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1448

Pin Definitions
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65 C to +150 C
Ambient Temperature with
Power Applied.............................................–55 C to +125 C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State ...........................–0.5V to V
DC Input Voltage......................................–0.5V to V
Document #: 38-06056 Rev. **
A
ADS
CE
CLK
CNTEN
CNTRST
I/O
LB
UB
OE
R/W
FT/PIPE
GND
NC
V
0L
CC
Left Port
L
0L
0L
L
L
–A
L
L
L
–I/O
,CE
15L
L
L
1L
L
17L
A
ADS
CE
CLK
CNTEN
CNTRST
I/O
LB
UB
OE
R/W
FT/PIPE
Right Port
0R
R
0R
0R
R
R
–A
R
R
R
–I/O
,CE
15R
R
R
R
1R
17R
Address Inputs (A
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads the
burst counter with the address present on the address pins.
Chip Enable Input. To select either the left or right port, both CE
to their active states (CE
Clock Signal. This input can be free running or strobed. Maximum clock input rate is f
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respec-
tive port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data Bus Input/Output (I/O
Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the
lower byte. (I/O
the LB and OE signals must be asserted to drive output data on the lower byte of the data pins.
Upper Byte Select Input. Same function as LB, but to the upper byte (I/O
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
Ground Input.
No Connect.
Power Input.
0
–I/O
0
–A
CC
CC
8
14
for x18, I/O
+0.5V
+0.5V
for 32K, A
0
0
–I/O
V
IL
and CE
15
0
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >1100V
Latch-Up Current...................................................... >200mA
Operating Range
–I/O
Commercial
Industrial
0
for x16 devices).
–A
7
13
Range
1
for x16) of the memory array. For read operations both
Description
for 16K devices).
V
IH
).
–40 C to +85 C
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Temperature
0 C to +70 C
Ambient
0
AND CE
8/9L
1
must be asserted
–I/O
3.3V
3.3V
15/17L
Page 4 of 19
V
CC
300 mV
300 mV
MAX
).
.