IDT7026L15JG IDT, Integrated Device Technology Inc, IDT7026L15JG Datasheet
IDT7026L15JG
Specifications of IDT7026L15JG
800-1366
800-1366-5
800-1366
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IDT7026L15JG Summary of contents
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... Features True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 15/20/25/35/55ns (max.) – Industrial: 20/25/35/55ns (max.) – Military: 20/25/35/55ns (max.) Low-power operation – IDT7026S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7026L Active: 750mW (typ.) Standby: 1mW (typ ...
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... This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down Pin Configurations (1,2,3) 11/16/01 ...
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IDT7026S/L High-Speed 16K x 16 Dual-Port Static RAM Pin Configurations (1,2,3) 11/16/ I/O I I/O I/O 10L I/O I/O 11L I/O I/O 13L 12L ...
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IDT7026S/L High-Speed 16K x 16 Dual-Port Static RAM Truth Table I – Non-Contention Read/Write Control (1) Inputs R ...
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IDT7026S/L High-Speed 16K x 16 Dual-Port Static RAM Recommended DC Operating Conditions Symbol Parameter V Supply Voltage CC GND Ground V Input High Voltage IH V Input Low Voltage -0.5 IL NOTES > -1.5V for pulse width less ...
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IDT7026S/L High-Speed 16K x 16 Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter Dynamic Operating Current CC SEM = V (Both Ports Active ...
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IDT7026S/L High-Speed 16K x 16 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA (3) t Chip Enable Access Time ACE (3) ...
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IDT7026S/L High-Speed 16K x 16 Dual-Port Static RAM WAVEFORM OF READ CYCLES ADDR CE OE UB, LB R/W DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends ...
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IDT7026S/L High-Speed 16K x 16 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Symbol WRITE CYCLE t Write Cycle Time WC t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW (3) t ...
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... ( and R for memory array writing cycle the end of write cycle. IH transition, the outputs remain in the High-impedance state during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the IH and SEM = V IH 6.42 10 (1,5,8) (7) ...
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IDT7026S/L High-Speed 16K x 16 Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side A -A VALID ADDRESS SEM I R/W OE NOTES ...
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IDT7026S/L High-Speed 16K x 16 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol BUSY TIMING (M/S BUSY Access Time from Address Match t BAA BUSY Disable Time from Address Not Matched ...
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IDT7026S/L High-Speed 16K x 16 Dual-Port Static RAM Timing Waveform of Write with Port-to-Port Read and BUSY (M ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ...
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IDT7026S/L High-Speed 16K x 16 Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing (M ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled by Address ...
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... The IDT7026 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected ( When a port is enabled, access to the entire memory array is permitted. Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “ ...
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... The eight semaphore flags reside within the IDT7026 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM ...
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... Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “ ...
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IDT7026S/L High-Speed 16K x 16 Dual-Port Static RAM Ordering Information XXXXX A 999 A Device Power Speed Package Type Datasheet Document History 1/14/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 and 3 Added ...