MC68HC908QY1MDW Freescale Semiconductor, MC68HC908QY1MDW Datasheet - Page 133

• Manufacturer Part Number: MC68HC908QY1MDW
• Description: 8-bit Microcontrollers - MCU 8 Bit 8MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908QY1MDW

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: HC08
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 1.5 KB
• Data Ram Size: 128 B
• On-chip Adc: No
• Operating Supply Voltage: 3.3 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: SOIC-16
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 13
• Number Of Timers: 2
• Program Memory Type: Flash
• Factory Pack Quantity: 47
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

Chapter 15
Development Support
15.1 Introduction
This section describes the break module, the monitor read-only memory (MON), and the monitor mode
entry methods.
15.2 Break Module (BRK)
The break module can generate a break interrupt that stops normal program flow at a defined address to
enter a background program.
Features include:
15.2.1 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal (BKPT) to the system integration module (SIM). The SIM then causes the CPU
to load the instruction register with a software interrupt instruction (SWI). The program counter vectors to
$FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
When a CPU generated address matches the contents of the break address registers, the break interrupt
is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and
returns the microcontroller unit (MCU) to normal operation.
Figure 15-2
Freescale Semiconductor
•
•
•
•
•
•
Accessible input/output (I/O) registers during the break Interrupt
Central processor unit (CPU) generated break interrupts
Software-generated break interrupts
Computer operating properly (COP) disabling during break interrupts
A CPU generated address (the address in the program counter) matches the contents of the break
address registers.
Software writes a 1 to the BRKA bit in the break status and control register.
shows the structure of the break module.
MC68HC908QY/QT Family Data Sheet, Rev. 6
133