MC68HC908QY1MDW Freescale Semiconductor, MC68HC908QY1MDW Datasheet - Page 76

• Manufacturer Part Number: MC68HC908QY1MDW
• Description: 8-bit Microcontrollers - MCU 8 Bit 8MHz
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC908QY1MDW

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: HC08
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 1.5 KB
• Data Ram Size: 128 B
• On-chip Adc: No
• Operating Supply Voltage: 3.3 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: SOIC-16
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 13
• Number Of Timers: 2
• Program Memory Type: Flash
• Factory Pack Quantity: 47
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 2.7 V

External Interrupt (IRQ)
8.4 Interrupts
The following IRQ source can generate interrupt requests:
8.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
8.5.1 Wait Mode
The IRQ module remains active in wait mode. Clearing IMASK in INTSCR enables IRQ interrupt requests
to bring the MCU out of wait mode.
8.5.2 Stop Mode
The IRQ module remains active in stop mode. Clearing IMASK in INTSCR enables IRQ interrupt requests
to bring the MCU out of stop mode.
8.6 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the
second step clears the status bit.
8.7 I/O Signals
The IRQ module shares its pin with the keyboard interrupt, input/output ports, and timer interface
modules.
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Interrupt flag (IRQF) — The IRQF bit is set when the IRQ pin is asserted based on the IRQ mode.
The IRQ interrupt mask bit, IMASK, is used to enable or disable IRQ interrupt requests.
When the IRQ function is enabled in the CONFIG2 register, the BIH and BIL
instructions can be used to read the logic level on the IRQ pin. If the IRQ
function is disabled, these instructions will behave as if the IRQ pin is a
logic 1, regardless of the actual level on the pin. Conversely, when the IRQ
function is enabled, bit 2 of the port A data register will always read a 0.
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine. An internal pullup
resistor to V
the IRQPUD bit in the CONFIG2 register ($001E).
DD
is connected to the IRQ pin; this can be disabled by setting
Chapter 13 System Integration Module (SIM).
MC68HC908QY/QT Family Data Sheet, Rev. 6
NOTE
Freescale Semiconductor