24LCS22A-I/SN Microchip Technology, 24LCS22A-I/SN Datasheet - Page 6

• Manufacturer Part Number: 24LCS22A-I/SN
• Description: IC EEPROM 2KBIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24LCS22A-I/SN

• Memory Size: 2K (256 x 8)
• Package / Case: 8-SOIC (3.9mm Width)
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 100kHz, 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 256 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.1 MHz
• Access Time: 3500 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 24LCS22A-I/SNG; 24LCS22A-I/SNG; 24LCS22AI/SN

24LCS22A
FIGURE 3-3:
DS21682E-page 6
Note 1: The base flowchart is copyright © 1993, 1994, 1995 Video Electronic Standard Association (VESA) from
DDC Circuit Powered
Display Power-on
2: The dash box and text “The 24LCS22A and... inside dash box.” are added by Microchip Technology Inc.
3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LCS22A.
from +5 volts
VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.
or
No
No
No
DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA
No
Send EDID™ continuously
Switch to DDC2™ mode.
Reset Vsync counter = 0
Increment VCLK counter
Switch back to DDC1™
Set Vsync counter = 0
using Vsync as clock
Stop sending EDID.
transition on SCL
Communication
Counter=128 or
transition state
DDC2 address
(if appropriate)
timer expired?
SCL, SDA or
or start timer
transition on
VCLK lines?
Display has
High-to-low
Change on
Yes
received?
Is Vsync
present?
High-low
optional
VCLK
cycle?
mode.
is idle
SCL?
Valid
?
?
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
Yes
No
Reset counter or timer
specification to determine
idle. Display waiting for
DDC2 communication
The 24LCS22A was designed to
comply to the portion of flowchart inside dash box
See Access.bus
correct procedure.
Valid Access.bus
address byte.
Access.bus™
transition on
High-to-low
received?
Is display
address?
capable?
address
DDC2B
SCL?
Yes
No
Yes
Yes
No
No
© 2009 Microchip Technology Inc.
Yes
No
Respond to DDC2B
Receive DDC2B
command
command
®