PCF8598C-2T/02,118 NXP Semiconductors, PCF8598C-2T/02,118 Datasheet
PCF8598C-2T/02,118
Specifications of PCF8598C-2T/02,118
PCF8598C2D-T
PCF8598C2D-T
Related parts for PCF8598C-2T/02,118
PCF8598C-2T/02,118 Summary of contents
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... PCF8598C-2 1024 Rev. 06 — 22 October 2004 1. Description The PCF8598C floating gate Electrically Erasable Programmable Read Only Memory (EEPROM) with 8 kbits (1024 internal redundant storage code fault tolerant to single bit errors. This feature dramatically increases the reliability compared to conventional EEPROMs. Power consumption is low due to the full CMOS technology used. The programming voltage is generated on-chip, using a voltage multiplier ...
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... DD Ordering information Package Name Description DIP8 plastic dual in-line package; 8 leads (300 mil) SO8 plastic small outline package 8 leads; body width 7.5 mm Ordering options Topside mark PCF8598C-2 8598C-2 Rev. 06 — 22 October 2004 PCF8598C-2 2 C-bus interface Min Typ Max Unit 2.5 - 6.0 ...
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... PCF8598C-2 6 SCL INPUT 5 FILTER SDA n ADDRESS SHIFT SWITCH REGISTER 3 A2 TEST MODE DECODER POWER-ON-RESET Fig 1. Block diagram C-BUS CONTROL LOGIC ADDRESS BYTE HIGH COUNTER REGISTER 3 BYTE 4 ADDRESS LATCH EEPROM 8 POINTER (8 bytes) ...
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... Rev. 06 — 22 October 2004 PCF8598C-2 2 C-bus interface PTC SCL 6 5 SDA 2 C-bus) 2 C-bus) © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... The Most Significant Bit (MSB) ‘b7’ is sent first the hardware selectable pin, A1 and A0 are software selectable pins. A system could have up to two PCF8598C-2 devices on the same kbit EEPROM devices of 1024 bytes of memory pages of 256 bytes of memory. A1 and A0 select a 256 byte page (one of the four pages available) on the selected device ...
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... Data transfer is unlimited in the read mode. The information is transmitted in bytes and each receiver acknowledges with a ninth bit. Within the I fast-speed mode (400 kHz clock rate) are defined. The PCF8598C-2 operates in only the standard-speed mode. By definition, a device that sends a signal is called a ‘transmitter’, and the device which receives the signal is called a ‘ ...
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... EEPROM if the pin WP is HIGH. When the pin WP is HIGH the upper 512 bytes of the EEPROM are write-protected and no acknowledge will be given by the PCF8598C-2 when data is sent. However, an acknowledge will be given after the slave address and the word address. Byte/word write: fi ...
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... Fig 5. Auto-increment memory word address; two byte write. Page write: initiated in the same manner as the byte write operation. The master can transit eight data bytes within one transmission. After receipt of each byte, the PCF8598C-2 will respond with an acknowledge. The typical E/W time in this mode ...
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... S SLAVE ADDRESS 0 A R/W Fig 7. Master reads PCF8598C-2 slave after setting word address (write word address; read data); sequential read. S SLAVE ADDRESS Fig 8. Master reads PCF8598C-2 immediately after first byte (read mode); current address read. 9397 750 14219 ...
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... Z > 500 V 0 Conditions Min 2 100 kHz SCL 100 kHz SCL 0.8 0.9V DD 0.8 0. Rev. 06 — 22 October 2004 PCF8598C-2 2 C-bus interface Max Unit +6 +150 C +85 C Typ Max Unit - 6 200 100 kHz - ...
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... Product data 1024 8-bit CMOS EEPROM with I Conditions Min 0 DD(min amb ; see Figure 9. DD Conditions repeated start Rev. 06 — 22 October 2004 PCF8598C-2 2 C-bus interface Typ Max Unit - years and V IL Min Max Unit 0 100 kHz 4.7 4.0 4.7 4 ...
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... HD;DAT SU;DAT 2 C-bus. Conditions internal oscillator external clock +85 C amb amb HIGH t LOW 1 2 STOP Rev. 06 — 22 October 2004 PCF8598C-2 2 C-bus interface t HD;STA SU;STA SU;STO MBA705 Min Typ Max 100000 1000000 257 MBA697 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... CMOS EEPROM with HIGH t LOW 1 2 STOP HIGH t LOW 1 2 STOP A DATA A DATA negative edge SCL 8-bit Rev. 06 — 22 October 2004 PCF8598C-2 2 C-bus interface n x 256 + 1 MBA698 1153 MBA699 A P (1) undefined 1 2 257 clock ( 513 clock ( 1153 clock ( MBA700 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... REFERENCES JEDEC JEITA MO-001 SC-504-8 Rev. 06 — 22 October 2004 PCF8598C-2 2 C-bus interface SOT97 ( max. 3.60 8.25 10.0 7.62 0.254 1.15 3 ...
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... 0.32 7.65 7.6 10.65 1.27 1.45 0.23 7.45 7.4 10.00 0.013 0.30 0.30 0.419 0.05 0.057 0.009 0.29 0.29 0.394 REFERENCES JEDEC JEITA Rev. 06 — 22 October 2004 PCF8598C-2 2 C-bus interface SOT176 detail ( 1.1 1.1 2.0 0.25 0.25 0.1 0.45 1.0 1 ...
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... C (SnPb process) or below 245 C (Pb-free process) – for all the BGA and SSOP-T packages 9397 750 14219 Product data 1024 8-bit CMOS EEPROM with I Rev. 06 — 22 October 2004 PCF8598C-2 2 C-bus interface ). stg(max) © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 9397 750 14219 Product data 1024 8-bit CMOS EEPROM with I 2 called small/thin packages. Rev. 06 — 22 October 2004 PCF8598C-2 2 C-bus interface 3 350 mm so called © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS [7] PLCC , SO, SOJ suitable LQFP, QFP, TQFP not recommended SSOP, TSSOP, VSO, not recommended VSSOP Rev. 06 — 22 October 2004 PCF8598C-2 2 C-bus interface [2] Reflow Dipping [3] suitable not suitable suitable [6] suitable suitable [7][8] ...
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... Product data; initial version (as PCF85xxC-2 family , 9397 750 01773). 9397 750 14219 Product data 1024 8-bit CMOS EEPROM with I 6, third paragraph: changed “high-speed” to Rev. 06 — 22 October 2004 PCF8598C-2 2 C-bus interface © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Licenses Purchase of Philips I Rev. 06 — 22 October 2004 PCF8598C-2 2 C-bus interface 2 C components 2 Purchase of Philips I ...
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... Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 22 October 2004 Document order number: 9397 750 14219 PCF8598C-2 1024 8-bit CMOS EEPROM with I 2 C-bus interface ...