MT45W1MW16PDGA-70 IT TR Micron Technology Inc, MT45W1MW16PDGA-70 IT TR Datasheet - Page 16

• Manufacturer Part Number: MT45W1MW16PDGA-70 IT TR
• Description: IC PSRAM 16MBIT 70NS 48VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W1MW16PDGA-70 IT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 16M (1M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VFBGA
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 12:
Partial-Array Refresh (CR[2:0]) Default = Full-Array Refresh
Sleep Mode (CR[4]) Default = PAR Enabled, DPD Disabled
Temperature-Compensated Refresh (CR[6:5]) Default = On-Chip Temperature Sensor
PDF: 09005aef81cadc83/Source:09005aef81c6edb4
16mb_asyncpage_cr1_0_p23z_2.fm - Rev. F 4/08 EN
CR[7]
0
1
CR[6] CR[5]
1
0
1
0
Configuration Register Bit Mapping
All must be set to "0"
Page Mode Disabled (default)
Page Mode Enabled
1
0
1
0
Page Mode Enable/Disable
RESERVED
+15˚C
+85˚C
Internal sensor (default)
+45˚C
Maximum Case Temp.
A[19:8]
19–8
The PAR bits restrict refresh operation to a portion of the total memory array. This fea-
ture allows the system to reduce current by only refreshing that part of the memory array
required by the host system. The refresh options are full array, one-half array, one-quar-
ter array, one-eighth array, or none of the array. The mapping of these partitions can
start at either the beginning or the end of the address map (see Table 3 on page 17).
The sleep mode bit determines which low-power mode is to be entered when ZZ# is
driven LOW. If CR[4] = 1, PAR operation is enabled. If CR[4] = 0, DPD operation is
enabled. PAR can also be enabled directly by writing to the CR using the software access
sequence. Note that this then disables ZZ# initiation of PAR. DPD cannot be enabled or
disabled using the software access sequence; this should only be done using ZZ# to
access the CR.
DPD operation disables all refresh-related activity. This mode will be used when the sys-
tem does not require the storage provided by the CellularRAM device. Any stored data
will become corrupted when DPD is enabled. When refresh activity has been re-enabled,
the CellularRAM device will require 150µs to perform an initialization procedure before
normal operation can resume. DPD should not be enabled using CR software access.
This CellularRAM device includes an on-chip temperature sensor that automatically
adjusts the refresh rate according to the operating temperature. The on-chip TCR is
enabled by clearing both of the TCR bits in the refresh configuration register (CR[6:5] =
00b). Any other TCR setting enables a fixed refresh rate. When the on-chip temperature
sensor is enabled, the device continually adjusts the refresh rate according to the operat-
ing temperature.
PAGE
7
A7
16Mb: 1 Meg x 16 Async/Page CellularRAM 1.0 Memory
6
A6
TCR
5
A5
SLEEP
CR[4]
0
1
4
A4
Must be set to "0"
16
RESERVED
DPD Enabled
PAR Enabled (default)
3
A3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Sleep Mode
CR[2]
Configuration Register Operation
2
A2
0
0
0
0
1
1
1
1
CR[1] CR[0]
0
0
1
1
0
0
1
1
PAR
1
A1
0
1
0
1
0
1
0
1
Full array (default)
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
None of array
Top 1/2 array
Top 1/4 array
Top 1/8 array
PAR Refresh Coverage
0
A0
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