MT48LC16M16A2P-6A:D TR Micron Technology Inc, MT48LC16M16A2P-6A:D TR Datasheet - Page 6

• Manufacturer Part Number: MT48LC16M16A2P-6A:D TR
• Description: IC SDRAM 256MBIT 167MHZ 54TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT48LC16M16A2P-6A:D TR

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-TSOP II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1223-2; MT48LC16M16A2P-6A:D TR

256Mb: x4, x8, x16 SDRAM
List of Figures
Figure 1: 64 Meg x 4 Functional Block Diagram ................................................................................................ 9
Figure 2: 32 Meg x 8 Functional Block Diagram .............................................................................................. 10
Figure 3: 16 Meg x 16 Functional Block Diagram ............................................................................................. 11
Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 12
Figure 5: 60-Ball FBGA (Top View) ................................................................................................................. 13
Figure 6: 54-Ball VFBGA (Top View) ............................................................................................................... 14
Figure 7: 54-Pin Plastic TSOP (400 mil) ........................................................................................................... 16
Figure 8: 60-Ball FBGA "FB" (8mm x 16mm) (x4, x8) ....................................................................................... 17
Figure 9: 54-Ball VFBGA "FG" (8mm x 14mm) (x16) ........................................................................................ 18
Figure 10: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) .............................................. 20
Figure 11: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) ........................................... 21
Figure 12: Example: Temperature Test Point Location, 60-Ball FBGA (Top View) ............................................. 21
Figure 13: ACTIVE Command ........................................................................................................................ 33
Figure 14: READ Command ........................................................................................................................... 34
Figure 15: WRITE Command ......................................................................................................................... 35
Figure 16: PRECHARGE Command ................................................................................................................ 36
Figure 17: Initialize and Load Mode Register .................................................................................................. 45
Figure 18: Mode Register Definition ............................................................................................................... 47
Figure 19: CAS Latency .................................................................................................................................. 50
t
t
t
Figure 20: Example: Meeting
RCD (MIN) When 2 <
RCD (MIN)/
CK < 3 ......................................................... 51
Figure 21: Consecutive READ Bursts .............................................................................................................. 53
Figure 22: Random READ Accesses ................................................................................................................ 54
Figure 23: READ-to-WRITE ............................................................................................................................ 55
Figure 24: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 56
Figure 25: READ-to-PRECHARGE .................................................................................................................. 56
Figure 26: Terminating a READ Burst ............................................................................................................. 57
Figure 27: Alternating Bank Read Accesses ..................................................................................................... 58
Figure 28: READ Continuous Page Burst ........................................................................................................ 59
Figure 29: READ – DQM Operation ................................................................................................................ 60
Figure 30: WRITE Burst ................................................................................................................................. 61
Figure 31: WRITE-to-WRITE .......................................................................................................................... 62
Figure 32: Random WRITE Cycles .................................................................................................................. 63
Figure 33: WRITE-to-READ ............................................................................................................................ 63
Figure 34: WRITE-to-PRECHARGE ................................................................................................................. 64
Figure 35: Terminating a WRITE Burst ........................................................................................................... 65
Figure 36: Alternating Bank Write Accesses .................................................................................................... 66
Figure 37: WRITE – Continuous Page Burst .................................................................................................... 67
Figure 38: WRITE – DQM Operation ............................................................................................................... 68
Figure 39: READ With Auto Precharge Interrupted by a READ ......................................................................... 70
Figure 40: READ With Auto Precharge Interrupted by a WRITE ....................................................................... 71
Figure 41: READ With Auto Precharge ............................................................................................................ 72
Figure 42: READ Without Auto Precharge ....................................................................................................... 73
Figure 43: Single READ With Auto Precharge .................................................................................................. 74
Figure 44: Single READ Without Auto Precharge ............................................................................................. 75
Figure 45: WRITE With Auto Precharge Interrupted by a READ ....................................................................... 76
Figure 46: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 76
Figure 47: WRITE With Auto Precharge .......................................................................................................... 77
Figure 48: WRITE Without Auto Precharge ..................................................................................................... 78
Figure 49: Single WRITE With Auto Precharge ................................................................................................ 79
Figure 50: Single WRITE Without Auto Precharge ........................................................................................... 80
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256Mb_sdr.pdf - Rev. N 1/10 EN
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