MT48LC8M16LFB4-8 IT:G Micron Technology Inc, MT48LC8M16LFB4-8 IT:G Datasheet - Page 42

• Manufacturer Part Number: MT48LC8M16LFB4-8 IT:G
• Description: IC SDRAM 128MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48LC8M16LFB4-8 IT:G

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-VFBGA
• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 19/8/7ns
• Maximum Clock Rate: 125MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 100mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 33:
Figure 34:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. L 10/07 EN
WRITE With Auto Precharge Interrupted by a READ
WRITE With Auto Precharge Interrupted by a WRITE
Internal
States
Internal
States
Notes:
Notes:
COMMAND
COMMAND
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
1. DQM is LOW.
1. DQM is LOW.
CLK
CLK
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after
valid data WRITE to bank n will be data registered 1 clock prior to a WRITE to bank m
(Figure 34).
DQ
DQ
t
WR is met, where
Page Active
Page Active
T0
NOP
T0
NOP
WRITE - AP
WRITE - AP
BANK n,
BANK n,
Page Active
Page Active
BANK n
BANK n
COL a
COL a
T1
D
T1
D
a
a
IN
IN
WRITE with Burst of 4
WRITE with Burst of 4
a + 1
a + 1
T2
T2
D
D
NOP
NOP
IN
IN
t
WR begins when the WRITE to bank m is registered. The last
42
BANK m,
READ - AP
a + 2
T3
COL d
T3
BANK m
D
NOP
IN
Interrupt Burst, Write-Back
t
WR - BANK n
READ with Burst of 4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BANK m,
TRANSITIONING DATA
WRITE - AP
TRANSITIONING DATA
COL d
BANK m
T4
T4
D
NOP
CL = 3 (BANK m)
t
d
IN
WR - BANK n
Interrupt Burst, Write-Back
WRITE with Burst of 4
128Mb: x16, x32 Mobile SDRAM
T5
T5
d + 1
NOP
NOP
D
IN
Precharge
t
RP - BANK n
T6
T6
d + 2
D
NOP
D
NOP
OUT
t RP - BANK n
d
IN
Precharge
DON’T CARE
DON’T CARE
©2001 Micron Technology, Inc. All rights reserved.
T7
T7
d + 3
D
d + 1
NOP
NOP
D
t WR - BANK m
t RP - BANK m
OUT
IN
Write-Back
READs