IS42S32400B-7BI ISSI, Integrated Silicon Solution Inc, IS42S32400B-7BI Datasheet
IS42S32400B-7BI
Specifications of IS42S32400B-7BI
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IS42S32400B-7BI Summary of contents
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... Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply DDQ IS42S32400B 3.3V 3.3V • LVTTL interface • Programmable burst length – ( full page) • Programmable burst sequence: Sequential/Interleave • Auto Refresh (CBR) • ...
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... IS42S32400B DEVICE OVERVIEW The 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V V and 3.3V V memory systems containing 134,217,728 DDQ bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 33,554,432-bit bank is orga- nized as 4,096 rows by 256 columns by 32 bits. ...
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... IS42S32400B PIN CONFIGURATIONS 86 pin TSOP - Type II for x32 V DD DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM0 WE CAS RAS CS A11 BA0 BA1 A10 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 V DD PIN DESCRIPTIONS A0-A11 Row Address Input A0-A7 ...
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... IS42S32400B PIN CONFIGURATION PACKAGE CODE BALL FBGA (Top View) (8. 13.00 mm Body, 0.8 mm Ball Pitch PIN DESCRIPTIONS A0-A11 Row Address Input A0-A7 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ31 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select ...
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... IS42S32400B PIN FUNCTIONS Symbol Type A0-A11 Input Pin BA0, BA1 Input Pin CAS Input Pin CKE Input Pin CLK Input Pin CS Input Pin DQM0-DQM3 Input Pin DQ0-DQ31 Input/Output Pin RAS Input Pin WE Input Pin V Power Supply Pin DDQ V Power Supply Pin ...
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... IS42S32400B GENERAL DESCRIPTION READ The READ command selects the bank from BA0, BA1 inputs and starts a burst read access to an active row. Inputs A0-A7 provides the starting column location. When A10 is HIGH, this command functions as an AUTO PRECHARGE command. When the auto precharge is selected, the row being accessed will be precharged at the end of the READ burst ...
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... IS42S32400B COMMAND TRUTH TABLE CKE Function n – 1 Device deselect (DESL operation (NOP) H Burst stop (BST) H Read H Read with auto precharge H Write H Write with auto precharge H Bank activate (ACT) H Precharge select bank (PRE) H Precharge all banks (PALL) H CBR Auto-Refresh (REF) H Self-Refresh (SELF) ...
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... IS42S32400B CKE TRUTH TABLE Current State /Function Activating Clock suspend mode entry Any Clock suspend mode Clock suspend mode exit Auto refresh command Idle (REF) Self refresh entry Idle (SELF) Power down entry Idle Self refresh exit Power down exit Note: H=V ...
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... IS42S32400B FUNCTIONAL TRUTH TABLE RAS RAS RAS RAS RAS CAS CAS CAS CAS CAS Current State Idle Row Active Read Write Note: H Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code Integrated Silicon Solution, Inc. — www.issi.com — PRELIMINARY INFORMATION Rev. 00J ...
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... IS42S32400B FUNCTIONAL TRUTH TABLE Continued RAS RAS RAS CAS RAS RAS CAS CAS CAS CAS Current State Read with auto H × × Precharging Write with Auto H × × Precharge Precharging H × × Row Activating H × × Note: H Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code ...
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... IS42S32400B FUNCTIONAL TRUTH TABLE Continued RAS CAS RAS RAS RAS RAS CAS CAS CAS CAS Current State Write Recovering H × × Write Recovering H × × with Auto Precharge Refresh H × × Mode Register H × × Accessing × Note: H Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code ...
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... IS42S32400B CKE RELATED COMMAND TRUTH TABLE Current State Operation Self-Refresh (S.R.) INVALID, CLK ( would exit S.R. Self-Refresh Recovery Self-Refresh Recovery Illegal Illegal Maintain S.R. Self-Refresh Recovery Idle After t RC Idle After t RC Illegal Illegal Begin clock suspend next cycle Begin clock suspend next cycle ...
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... IS42S32400B STATE DIAGRAM Mode Register Set Write CKE WRITE WRITE SUSPEND CKE CKE WRITEA WRITEA SUSPEND CKE Precharge POWER ON Integrated Silicon Solution, Inc. — www.issi.com — PRELIMINARY INFORMATION Rev. 00J 03/03/09 SELF SELF exit MRS IDLE CKE CKE ACT CKE Row ...
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... IS42S32400B ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage DD MAX V Maximum Supply Voltage for Output Buffer DDQ MAX V Input Voltage IN V Output Voltage OUT P Allowable Power Dissipation D MAX I Output Shorted Current CS T Operating Temperature OPR T Storage Temperature STG Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
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... IS42S32400B DC ELECTRICAL CHARACTERISTICS 1 Symbol Parameter I Operating Current (1) DD1 I Precharge Standby Current DD2P (In Power-Down Mode) I Precharge Standby Current DD2PS (In Power-Down Mode) I Precharge Standby Current (2) DD2N (In Non Power-Down Mode) I Precharge Standby Current DD2NS (In Non Power-Down Mode) I Active Standby Current (2) DD3N (In Non Power-Down Mode) ...
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... IS42S32400B AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Clock Cycle Time CK3 t CK2 t Access Time From CLK AC3 t AC2 t CLK HIGH Level Width CHI t CLK LOW Level Width CL t Output Data Hold Time OH3 t OH2 t Output LOW Impedance Time LZ t Output HIGH Impedance Time ...
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... IS42S32400B OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency CAS Latency t CAC t Active Command To Read/Write Command Delay Time RCD RAS Latency ( RAC RCD CAC t Command Period (REF to REF / ACT to ACT Command Period (ACT to PRE) RAS t Command Period (PRE to ACT) ...
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... IS42S32400B AC TEST CONDITIONS Input Load t CHI 3.0V 1.4V CLK 3.0V INPUT 1. OUTPUT 1.4V AC TEST CONDITIONS Parameter AC Input Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Measurement Reference Level 18 Output Load 1.4V Integrated Silicon Solution, Inc. — www.issi.com — ...
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... IS42S32400B FUNCTIONAL DESCRIPTION The 128Mb SDRAMs are quad-bank DRAMs which operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; ...
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... IS42S32400B INITIALIZE AND LOAD MODE REGISTER CLK CKS CKH CKE CMH CMS CMH CMS COMMAND NOP PRECHARGE DQM0-DQM3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 ALL BANKS Power-up: V Precharge CC and CLK stable all banks T = 100µs Min. Notes High at clock High time, all commands applied are NOP. ...
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... IS42S32400B AUTO-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM0 - DQM3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK ( High-Z Notes: 1. CAS latency = 2, 3 Integrated Silicon Solution, Inc. — www.issi.com — PRELIMINARY INFORMATION Rev. 00J ...
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... IS42S32400B SELF-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM0 - DQM3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Precharge all active banks CKS ≥ t RAS Auto NOP Refresh t RP Enter self CLK stable prior to exiting ...
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... IS42S32400B REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power ...
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... IS42S32400B BURST LENGTH Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length deter- mines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst ...
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... IS42S32400B CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge ...
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... IS42S32400B CHIP OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). ...
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... IS42S32400B READS READ bursts are initiated with a READ command, as shown in the READ COMMAND diagram. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst ...
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... IS42S32400B possible CAS latency; data element either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until the row precharge time is hidden during the access of the last data element(s). ...
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... IS42S32400B RW1 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 2 RW2 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL n DQ Integrated Silicon Solution, Inc. — www.issi.com — PRELIMINARY INFORMATION Rev. 00J 03/03/ NOP NOP NOP NOP ...
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... IS42S32400B CONSECUTIVE READ BURSTS T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - NOP NOP NOP READ n+1 OUT OUT NOP NOP READ BANK, COL n+1 OUT OUT Integrated Silicon Solution, Inc. — www.issi.com — ...
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... IS42S32400B RANDOM READ ACCESSES T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com — PRELIMINARY INFORMATION Rev. 00J 03/03/ READ READ READ BANK, BANK, BANK, COL b COL m COL OUT ...
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... IS42S32400B READ BURST TERMINATION T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - NOP NOP NOP TERMINATE n+1 OUT OUT BURST NOP NOP TERMINATE n+1 OUT OUT Integrated Silicon Solution, Inc. — www.issi.com — ...
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... IS42S32400B ALTERNATING BANK READ ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK BANK 0 RCD t RRD t - BANK 0 RAS t - BANK 0 RC Notes: 1) CAS latency = 2, Burst Length = 4 2) X32: A8, A9, A11 = "Don't Care" ...
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... IS42S32400B READ - FULL-PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM0 - DQM3 A0-A9, A11 ROW COLUMN A10 ROW BA0, BA1 BANK BANK DQ t RCD Notes: 1) CAS latency = 2, Burst Length = Full Page 2) X32: A8, A9, A11 = "Don't Care" ...
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... IS42S32400B READ - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD Notes: 1) CAS latency = 2, Burst Length = 4 2) X32: A8, A9, A11 = "Don't Care" ...
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... IS42S32400B READ to PRECHARGE T0 T1 CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - NOP NOP PRECHARGE BANK (a or all n+1 D n+2 OUT OUT OUT NOP NOP PRECHARGE BANK, COL n+1 ...
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... IS42S32400B WRITES WRITE bursts are initiated with a WRITE command, as shown in WRITE Command diagram. WRITE COMMAND CLK HIGH CKE CS RAS CAS WE A0-A7 COLUMN ADDRESS A8, A9, A11 AUTO PRECHARGE A10 NO PRECHARGE BA0, BA1 BANK ADDRESS The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access ...
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... IS42S32400B WRITE BURST COMMAND ADDRESS WRITE TO WRITE RANDOM WRITE CYCLES COMMAND ADDRESS CLK WRITE NOP NOP BANK, COL n CLK COMMAND WRITE NOP BANK, ADDRESS COL n DON'T CARE CLK WRITE WRITE WRITE BANK, BANK, BANK, COL n COL b COL Integrated Silicon Solution, Inc. — www.issi.com — ...
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... IS42S32400B WRITE to READ T0 CLK COMMAND WRITE BANK, ADDRESS COL WP1 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL Integrated Silicon Solution, Inc. — www.issi.com — PRELIMINARY INFORMATION Rev. 00J 03/03/ NOP READ NOP BANK, COL n+1 IN CAS Latency - NOP NOP ...
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... IS42S32400B WP2 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS NOP NOP PRECHARGE BANK (a or all) t DPL D n CLK BURST WRITE TERMINATE BANK, (ADDRESS) COL DON'T CARE Integrated Silicon Solution, Inc. — www.issi.com — NOP ...
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... IS42S32400B WRITE - FULL PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1) Burst Length = Full Page 2) X32: A8, A9, A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com — ...
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... IS42S32400B WRITE - DQM OPERATION T0 t CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE DQM0 - DQM3 A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t Notes: 1) Burst Length = 4 2) X32: A8, A9, A11 = "Don't Care" NOP WRITE NOP NOP t t CMS CMH ...
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... IS42S32400B ALTERNATING BANK WRITE ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM0 - DQM3 A0-A9, A11 ROW COLUMN ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK BANK 0 RCD t RRD t - BANK 0 RAS t - BANK 0 RC Notes: 1) Burst Length = 4 2) X32: A8, A9, A11 = "Don't Care" ...
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... IS42S32400B CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. ...
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... IS42S32400B CLOCK SUSPEND MODE CLK CKS CKH CKE t t CMS CMH COMMAND READ NOP t t CMS CMH DQM0 - DQM3 (2) A0-A9, A11 COLUMN A10 BA0, BA1 BANK DQ Notes: 1) CAS latency = 3, Burst Length = 2, Auto Precharge is disabled. 2) X32: A8, A9, A11 = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com — ...
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... IS42S32400B PRECHARGE The PRECHARGE command (see figure) is used to deac- tivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (t ) after the PRECHARGE RP command is issued. Input A10 determines whether one or ...
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... IS42S32400B POWER-DOWN MODE CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM0 - DQM3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Two clock cycles Precharge all All banks idle, enter active banks power-down mode Note: X32: A8, A9, A11 = " ...
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... IS42S32400B BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation ( ...
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... IS42S32400B WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing (CAS latency) later. The PRECHARGE to bank n will begin after t where t begins when the READ to bank m is registered. ...
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... IS42S32400B SINGLE READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 1 2) X32: A8, A9, A11 = "Don't Care" ...
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... IS42S32400B READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 4 2) X32: A8, A9, A11 = "Don't Care" ...
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... IS42S32400B SINGLE READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW A10 ROW DISABLE AUTO PRECHARGE BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 1 2) X32: A8, A9, A11 = "Don't Care" ...
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... IS42S32400B READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 4 2) X32: A8, A9, A11 = "Don't Care" ...
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... IS42S32400B SINGLE WRITE - WITH AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 1 2) X32: A8, A9, A11 = "Don't Care" must not be violated. ...
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... IS42S32400B SINGLE WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW DISABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 1 2) X32: A8, A9, A11 = "Don't Care" ...
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... IS42S32400B WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 4 2) X32: A8, A9, A11 = "Don't Care" ...
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... IS42S32400B WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM0 - DQM3 A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK RCD t RAS t RC Notes: 1) Burst Length = 4 2) X32: A8, A9, A11 = "Don't Care" ...
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... IS42S32400B-6TI 166 MHz 6 IS42S32400B-6TLI 166 MHz 6 IS42S32400B-6BLI 143 MHz 7 IS42S32400B-7TI 143 MHz 7 IS42S32400B-7TLI 143 MHz 7 IS42S32400B-7BI 143 MHz 7 IS42S32400B-7BLI 58 = 3.3V DD Package 86-Pin TSOPII 86-Pin TSOPII, Lead-free 90-Ball FBGA 90-Ball FBGA, Lead-free 86-Pin TSOPII 86-Pin TSOPII, Lead-free 90-Ball FBGA 90-Ball FBGA, Lead-free = 3 ...
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