IS42S16320B-7TLI ISSI, Integrated Silicon Solution Inc, IS42S16320B-7TLI Datasheet

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... IS42S86400B IS42S16320B, IS45S16320B 64M x 8, 32M x 16 512Mb SYNCHRONOUS DRAM FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply ddq IS42/45S16320B 3.3V 3.3V IS42S86400B 3.3V 3.3V • LVTTL interface • Programmable burst length – ( full page) • Programmable burst sequence: Sequential/Interleave • ...

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... REFRESH COUNTER 8192 8192 8192 13 ROW ADDRESS BUFFER 13 BANK CONTROL LOGIC Integrated Silicon Solution, Inc. — www.issi.com DQML DQMH DATA IN BUFFER 0- DDQ DATA OUT BUFFER Q 16 8192 MEMORY CELL ARRAY BANK 0 SENSE AMP I/O GATE 1024 (x 16) COLUMN DECODER 10 Rev. G 04/08/2011 ...

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IS42S86400B, IS42/45S16320B PIN CONFIGURATIONS 54 pin TSOP - Type II for x8 PIN DESCRIPTIONS A0-A12 Row Address Input A0-A9, A11 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ7 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command CAS Column Address Strobe Command Integrated Silicon Solution, ...

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IS42S86400B, IS42/45S16320B PIN CONFIGURATIONS 54 pin TSOP - Type II for x16 PIN DESCRIPTIONS A0-A12 Row Address Input A0-A9 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ15 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command Column Address Strobe Command CAS 4 V ...

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IS42S86400B, IS42/45S16320B PIN CONFIGURATION 54-ball W-BGA for x16 (Top View) (11. 13.00 mm Body, 0.8 mm Ball Pitch) package code: B PIN DESCRIPTIONS A0-A12 Row Address Input A0-A9 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ15 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command CAS Column Address Strobe Command ...

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... P ower Supply Pin ss 6 Function (In Detail) Address Inputs: A0-A12 are sampled during the ACTIVE command (row-address A0-A12) and READ/WRITE command (column address A0-A9 (x16); A0-A9, A11 (x8); with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. CAS, in conjunction with the RAS and WE, forms the device command. See the " ...

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... The row being accessed will be precharged at the end of the WRITE burst, if AUTO PRECHARGE is selected. If AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. A memory array is written with corresponding input data on DQ’s and DQM input logic level appearing at the same time. Data will be written to memory when DQM signal is LOW. When DQM is HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. ...

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IS42S86400B, IS42/45S16320B COMMAND TRUTH TABLE CKE Function n – 1 Device deselect (DESL operation (NOP) H Burst stop (BST) H Read H Read with auto precharge H Write H Write with auto precharge H Bank activate (ACT) H Precharge select bank (PRE) H Precharge all banks (PALL) H CBR Auto-Refresh (REF) H ...

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IS42S86400B, IS42/45S16320B CKE TRUTH TABLE Current State /Function Activating Clock suspend mode entry Any Clock suspend mode Clock suspend mode exit Auto refresh command Idle (REF) Self refresh entry Idle (SELF) Power down entry Idle Self refresh exit Power down exit Note: H Valid Data Integrated Silicon Solution, Inc. — www.issi.com Rev. G 04/08/2011 CKE n – ...

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IS42S86400B, IS42/45S16320B FUNCTIONAL TRUTH TABLE Current State CS RAS CAS WE Idle ...

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IS42S86400B, IS42/45S16320B FUNCTIONAL TRUTH TABLE Continued: Current State CS RAS CAS WE Read with auto H × × Precharging L L ...

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IS42S86400B, IS42/45S16320B FUNCTIONAL TRUTH TABLE Continued: Current State CS RAS CAS WE Write Recovering H × × ...

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IS42S86400B, IS42/45S16320B CKE RELATED COMMAND TRUTH TABLE Current State Operation Self-Refresh (S.R.) INVALID, CLK ( would exit S.R. Self-Refresh Recovery Self-Refresh Recovery Illegal Illegal Maintain S.R. Self-Refresh Recovery Idle After t rc Idle After t rc Illegal Illegal Begin clock suspend next cycle Begin clock suspend next cycle ...

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IS42S86400B, IS42/45S16320B STATE DIAGRAM Mode Register Set Write CKE WRITE WRITE SUSPEND CKE CKE WRITEA WRITEA SUSPEND CKE Precharge POWER ON 14 SELF SELF exit MRS IDLE CKE CKE ACT CKE Row Active CKE BST BST Read Write Read Write ...

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IS42S86400B, IS42/45S16320B ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage dd max V Maximum Supply Voltage for Output Buffer ddq max V Input Voltage in V Output Voltage out P Allowable Power Dissipation d max I output Shorted Current cs T operating Temperature opr ...

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IS42S86400B, IS42/45S16320B DC ELECTRICAL CHARACTERISTICS 1 Symbol Parameter i Operating Current (1) dd1 i Precharge Standby Current dd2p (In Power-Down Mode) i Precharge Standby Current dd2ps (In Power-Down Mode) i Precharge Standby Current (2) dd2n (In Non Power-Down Mode) I Precharge Standby Current dd2ns (In Non Power-Down Mode) ...

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... Refresh Cycle Time (8192) ref T ≤ Com., Ind ≤ Notes: 1. The power-on sequence must be executed before starting memory operation. 2. measured with ns. If clock rising time is longer than 1ns The reference level is 1.4V when measuring input signal timing. Rise and fall times are measured between V (max). 4. Self-Refresh Mode is not supported for A2 grade with T Integrated Silicon Solution, Inc. — www.issi.com Rev. G 04/08/2011 (1,2,3) -6 Min. Max. 6 — CAS Latency = 3 10 — CAS Latency = 2 — 5.4 CAS Latency = 3 — ...

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IS42S86400B, IS42/45S16320B OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency t CAS Latency cac t Active Command To Read/Write Command Delay Time rcd t RAS Latency ( rac rcd cac ...

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IS42S86400B, IS42/45S16320B AC TEST CONDITIONS Input Load t CH 3.0V 1.4V CLK CMS CMH 3.0V INPUT 1. OUTPUT 1.4V AC TEST CONDITIONS Parameter AC Input Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Measurement Reference Level Integrated Silicon Solution, Inc. — www.issi.com Rev. ...

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IS42S86400B, IS42/45S16320B FUNCTIONAL DESCRIPTION The 512Mb SDRAMs are quad-bank DRAMs which operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 134,217,728-bit banks is organized as 8,192 rows by 1024 columns by 16 bits or 8192 rows by 2048 columns by 8bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin ...

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IS42S86400B, IS42/45S16320B INITIALIzE AND LOAD MODE REGISTER CLK CKS CKH CKE CMS CMH CMS CMH COMMAND NOP PRECHARGE DQM/ DQML, DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, ...

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IS42S86400B, IS42/45S16320B AUTO-REFRESH CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK ( High-Z Notes: 1. ...

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IS42S86400B, IS42/45S16320B SELF-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Precharge ...

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IS42S86400B, IS42/45S16320B REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. MODE REGISTER DEFINITION BA1 BA0 A12 A11 A10 (1) Reserved Write Burst Mode ...

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IS42S86400B, IS42/45S16320B BURST LENGTH Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length deter- mines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, mean- ing that the burst will wrap within the block if a boundary BURST DEFINITION Burst Starting Column Length Address ...

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IS42S86400B, IS42/45S16320B CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge The DQs will start driving as a result of the clock edge one cycle earlier ( 1), and provided that the relevant access times are met, the data will be valid by clock edge For example, assuming that the clock cycle time is such that all relevant access times are met READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving ...

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IS42S86400B, IS42/45S16320B CHIP OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the t specification. Minimum t rcd rcd the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example specification of 15ns with a rcd 143 MHz clock (7ns period) results in 2.14 clocks, rounded to 3. This is reflected in the following example, which cov- ...

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IS42S86400B, IS42/45S16320B READS READ bursts are initiated with a READ command, as shown in the READ COMMAND diagram. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the fol- lowing illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. The CAS Latency diagram shows general timing for each possible CAS latency setting. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst ...

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IS42S86400B, IS42/45S16320B diagram for each possible CAS latency; data element either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until t is met. Note that part of the row precharge time is rp hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result ...

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IS42S86400B, IS42/45S16320B RW1 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 2 RW2 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL ...

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IS42S86400B, IS42/45S16320B CONSECUTIVE READ BURSTS T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. ...

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IS42S86400B, IS42/45S16320B RANDOM READ ACCESSES T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - READ READ READ BANK, BANK, BANK, COL b COL ...

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IS42S86400B, IS42/45S16320B READ BURST TERMINATION T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com ...

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IS42S86400B, IS42/45S16320B ALTERNATING BANK READ ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11, A12 ROW ENABLE AUTO ...

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IS42S86400B, IS42/45S16320B READ - FULL-PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMH A0-A9, A11, A12 ROW COLUMN m ...

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IS42S86400B, IS42/45S16320B READ - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11, A12 ROW ENABLE AUTO ...

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IS42S86400B, IS42/45S16320B READ to PRECHARGE T0 T1 CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. ...

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IS42S86400B, IS42/45S16320B WRITES WRITE bursts are initiated with a WRITE command, as shown in WRITE Command diagram. WRITE COMMAND CLK HIGH CKE CS RAS CAS WE A0-A9 COLUMN ADDRESS A11, A12 AUTO PRECHARGE A10 NO PRECHARGE BA0, BA1 BANK ADDRESS The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive posi- tive clock edge. Upon completion of a fixed-length burst, assuming no ...

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IS42S86400B, IS42/45S16320B WRITE BURST COMMAND ADDRESS WRITE TO WRITE RANDOM WRITE CYCLES COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com Rev. G 04/08/2011 CLK WRITE NOP NOP BANK, COL n ...

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IS42S86400B, IS42/45S16320B WRITE to READ T0 CLK COMMAND WRITE BANK, ADDRESS COL WP1 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL ...

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IS42S86400B, IS42/45S16320B WP2 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com Rev. G 04/08/2011 NOP ...

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IS42S86400B, IS42/45S16320B WRITE - FULL PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW ...

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IS42S86400B, IS42/45S16320B WRITE - DQM OPERATION T0 t CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW ...

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IS42S86400B, IS42/45S16320B ALTERNATING BANK WRITE ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t DQM/DQML DQMH A0-A9, A11, A12 ROW ENABLE AUTO ...

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IS42S86400B, IS42/45S16320B CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time Clock Suspend During WRITE Burst T0 CLK CKE INTERNAL CLOCK COMMAND NOP ADDRESS DQ Clock Suspend During READ Burst T0 CLK CKE INTERNAL CLOCK COMMAND READ BANK a, ADDRESS ...

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IS42S86400B, IS42/45S16320B CLOCK SUSPEND MODE CLK CKS CKH CKE t t CMS CMH COMMAND READ NOP t t CMS CMH DQM/DQML DQMH A0-A9, A11, A12 COLUMN m ( ...

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IS42S86400B, IS42/45S16320B PRECHARGE The PRECHARGE command (see figure) is used to deac- tivate the open row in a particular bank or the open row in all banks bank(s) will be available for a subsequent row access some specified time (t ) after the PRECHARGE rp command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. POWER-DOWN Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in either bank, this mode is referred to as active power-down. Entering power-down deactivates the input and ...

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IS42S86400B, IS42/45S16320B POWER-DOWN MODE CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/DQML DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Two clock cycles ...

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IS42S86400B, IS42/45S16320B BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0). CONCURRENT AUTO PRECHARGE An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. ISSI READ With Auto Precharge interrupted by a READ T0 T1 CLK READ - AP NOP COMMAND ...

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IS42S86400B, IS42/45S16320B WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing (CAS latency) later. The PRECHARGE to bank n will begin after t is met, where t begins when the READ to bank m is dpl registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. WRITE With Auto Precharge interrupted by a READ T0 T1 CLK WRITE - AP COMMAND NOP BANK n BANK ...

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IS42S86400B, IS42/45S16320B SINGLE READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW ...

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IS42S86400B, IS42/45S16320B SINGLE READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW ...

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IS42S86400B, IS42/45S16320B READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE ...

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IS42S86400B, IS42/45S16320B READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW t ...

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IS42S86400B, IS42/45S16320B SINGLE WRITE WITH AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM/DQML, DQMH A0-A9, A11, A12 ROW A10 ROW ...

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IS42S86400B, IS42/45S16320B SINGLE WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW DISABLE ...

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IS42S86400B, IS42/45S16320B WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/DQML DQMH A0-A9, A11, A12 ROW t t ...

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IS42S86400B, IS42/45S16320B WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/DQML DQMH A0-A9, A11, A12 ROW A10 ROW ...

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... IS42S86400B-75ETL IS42S16320B-75ETL Industrial Range: - +85 o Frequency Speed (ns) Order Part No. 166 MHz 6 IS42S86400B-6TLI IS42S16320B-6TLI IS42S16320B-6BLI 143 MHz 7 IS42S86400B-7TLI IS42S16320B-7TLI IS42S16320B-7BLI 133 MHz 7.5 IS42S86400B-75ETLI 54-Pin TSOPII, Alloy42 leadframe plated with matte Sn IS42S16320B-75ETLI 54-Pin TSOPII, Alloy42 leadframe plated with matte Sn Automotive Range: - +85 o Frequency Speed (ns) Order Part No. 166 MHz 6 IS45S16320B-6BLA1 143 MHz 7 IS45S16320B-7TLA1 IS45S16320B-7CTNA1 54-Pin TSOPII, Cu leadframe plated with NiPdAu ...

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IS42S86400B, IS42/45S16320B 60 Integrated Silicon Solution, Inc. — www.issi.com Rev. G 04/08/2011 ...

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IS42S86400B, IS42/45S16320B Integrated Silicon Solution, Inc. — www.issi.com Rev. G 04/08/2011 61 ...

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IS42S86400B, IS42/45S16320B 6.50 ±0.1 3. Integrated Silicon Solution, Inc. — www.issi.com 04/08/2011 Rev. G ...