IS42S16320B-7TLI ISSI, Integrated Silicon Solution Inc, IS42S16320B-7TLI Datasheet - Page 24

• Manufacturer Part Number: IS42S16320B-7TLI
• Description: IC SDRAM 512MBIT 143MHZ 54TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16320B-7TLI

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-TSOP II
• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 6.5/5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 130mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 143 MHz
• Access Time: 6.5 ns, 5.4 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 130 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

REGISTER command and will retain the stored information
IS42S86400B, IS42/45S16320B
REGISTER DEFINITION
Mode Register
The mode register is used to define the specific mode
of operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
MODE REGISTER DEFINITION.
The mode register is programmed via the LOAD MODE
until it is programmed again or the device loses power.
MODE REGISTER DEFINITION
24
BA1 BA0 A12
A11
Reserved
A10
Write Burst Mode
(1)
M9
0
1
A9
Mode
Programmed Burst Length
Single Location Access
Operating Mode
A8
M8 M7
— —
0
0
A7
Defined
M6-M0
—
A6
Latency Mode
M6 M5 M4
0
0
0
0
1
1
1
1
Mode
Standard Operation
All Other States Reserved
A5
0
0
1
1
0
0
1
1
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved), M4- M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the W RITE burst mode, and M10, M11,
and M12 are reserved for future use.
The mode register must be loaded when all banks are
idle, and the controller must wait the specified time before
initiating the subsequent operation. V iolating either of these
requirements will result in unspecified operation.
0
1
0
1
0
1
0
1
Integrated Silicon Solution, Inc. — www.issi.com
A4
Burst Type
CAS Latency
M3
0
1
A3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
Interleaved
Sequential
1. To ensure compatibility with future devices,
A2
Burst Length
Type
should program BA1, BA0, A12, A11, A10 = "0"
M2
0
0
0
0
1
1
1
1
A1
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
A0
Reserved
Reserved
Reserved
Address Bus (Ax)
Mode Register (Mx)
Full Page
M3=0
1
2
4
8
Reserved
Reserved
Reserved
Reserved
M3=1
1
2
4
8
04/08/2011
Rev. G