MT46H32M32LFCM-6 L IT:A Micron Technology Inc, MT46H32M32LFCM-6 L IT:A Datasheet - Page 32

• Manufacturer Part Number: MT46H32M32LFCM-6 L IT:A
• Description: IC DDR SDRAM 1GBIT 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H32M32LFCM-6 L IT:A

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 1G (32M x 32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Commands
Table 14: Truth Table – Commands
CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN; all states and sequences not shown
are reserved and/or illegal
PDF: 09005aef82ce3074
1gb_ddr_mobile_sdram_t48m.pdf - Rev. K 07/09 EN
Name (Function)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (select bank and activate row)
READ (select bank and column, and start READ burst)
WRITE (select bank and column, and start WRITE burst)
BURST TERMINATE or DEEP POWER-DOWN (enter deep
power-down mode)
PRECHARGE (deactivate row in bank or banks)
AUTO REFRESH (refresh all or single bank) or SELF RE-
FRESH (enter self refresh mode)
LOAD MODE REGISTER
Notes:
A quick reference for available commands is provided in Table 14 and Table 15
(page 33), followed by a written description of each command. Three additional truth
tables (Table 16 (page 39), Table 17 (page 40), and Table 18 (page 43)) provide CKE
commands and current/next state information.
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide bank address and A[0:I] provide row address (where I = the most signif-
3. BA0–BA1 provide bank address; A[0:I] provide column address (where I = the most signif-
4. Applies only to READ bursts with auto precharge disabled; this command is undefined
5. This command is a BURST TERMINATE if CKE is HIGH and DEEP POWER-DOWN if CKE is
6. A10 LOW: BA0–BA1 determine which bank is precharged.
7. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
8. Internal refresh counter controls row addressing; in self refresh mode all inputs and I/Os
9. BA0–BA1 select the standard mode register, extended mode register, or status register.
icant address bit for each configuration).
icant address bit for each configuration); A10 HIGH enables the auto precharge feature
(nonpersistent); A10 LOW disables the auto precharge feature.
and should not be used for READ bursts with auto precharge enabled and for WRITE bursts.
LOW.
A10 HIGH: all banks are precharged and BA0–BA1 are “Don’t Care.”
are “Don’t Care” except for CKE.
32
CS#
H
L
L
L
L
L
L
L
L
RAS#
1Gb: x16, x32 Mobile LPDDR SDRAM
X
H
H
H
H
Micron Technology, Inc. reserves the right to change products or specifications without notice.
L
L
L
L
CAS#
X
H
H
H
H
L
L
L
L
WE#
H
H
H
H
X
L
L
L
L
©2007 Micron Technology, Inc. All rights reserved.
Bank/column
Bank/column
Bank/row
Address
Op-code
Code
X
X
X
X
Commands
Notes
4, 5
7, 8
1
1
2
3
3
6
9