M28W320FCT70N6F NUMONYX, M28W320FCT70N6F Datasheet - Page 14

• Manufacturer Part Number: M28W320FCT70N6F
• Description: IC FLASH 32MBIT 70NS 48TSOP
• Manufacturer: NUMONYX

Specifications of M28W320FCT70N6F

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 32M (2M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3.1
3.2
3.3
3.4
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Bus operations
There are six standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby, Automatic Standby and Reset. See
Operations, for a summary.
Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the
memory and do not affect bus operations.
Read
Read Bus operations are used to output the contents of the Memory Array, the Electronic
Signature, the Status Register and the Common Flash Interface. Both Chip Enable and
Output Enable must be at V
should be used to enable the device. Output Enable should be used to gate data onto the
output. The data read depends on the previous command written to the memory (see
Command Interface section). See
Characteristics, for details of when the output becomes valid.
Read mode is the default state of the device when exiting Reset or after power-up.
Write
Bus Write operations write Commands to the memory or latch Input Data to be
programmed. A write operation is initiated when Chip Enable and Write Enable are at V
with Output Enable at V
edge of Write Enable or Chip Enable, whichever occurs first.
See
Characteristics, for details of the timing requirements.
Output Disable
The data outputs are high impedance when the Output Enable is at V
Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current
consumption. The memory is in stand-by when Chip Enable is at V
read mode. The power consumption is reduced to the stand-by level and the outputs are set
to high impedance, independently from the Output Enable or Write Enable inputs. If Chip
Enable switches to V
mode when finished.
Figure 9
and
Figure
IH
during a program or erase operation, the device enters Standby
IH
10, Write AC Waveforms, and
. Commands, Input Data and Addresses are latched on the rising
IL
in order to perform a read operation. The Chip Enable input
Figure 8: Read AC
Waveforms, and
Table 17
and
IH
Table 2: Bus
and the device is in
Table
IH
Table 16: Read AC
.
18, Write AC
IL