IDT70121S55J IDT, Integrated Device Technology Inc, IDT70121S55J Datasheet - Page 13

• Manufacturer Part Number: IDT70121S55J
• Description: IC SRAM 18KBIT 55NS 52PLCC
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT70121S55J

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 18K (2K x 9)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 52-PLCC
• Density: 18Kb
• Access Time (max): 55ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 22b
• Package Type: PLCC
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 240mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 52
• Word Size: 9b
• Number Of Words: 2K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 70121S55J

Timing Waveform of Interrupt Mode
Truth Tables
Truth Table I. Non-Contention Read/Write Control
Truth Table II. Interrupt Flag
NOTES:
1. Assumes BUSY
2. If BUSY
3. If BUSY
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
NOTES:.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
NOTES:
1. A
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see t
4. 'H' = V
ADDR
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
R/W
R/W
R/W
INT
X
X
H
H
0L
X
X
X
L
L
L
– A
'A'
'A'
'B'
IH
10L
L
R
, 'L' = V
= V
= V
≠ A
Left or Right Port
CE
IL
CE
IL
H
H
X
X
L
L
L
L
L
, then No Change.
, then No Change.
0R
L
L
IL
= BUSY
– A
, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
10R
Left Port
.
R
OE
OE
X
X
X
L
H
X
X
X
L
= V
L
t
AS
IH
INTERRUPT SET ADDRESS
(1)
(3)
A
DATA
DATA
10L
7FE
7FF
t
D
X
X
INS
WDD
-A
Z
Z
Z
0-8
OUT
0L
IN
(3)
and t
t
WC
DDD
Port Disab le and in Power-Down Mode, I
Data on Port Written Into Memory
Data in Memory Output on Port
High-Impedance Outputs
CE
INT
L
H
X
X
R
(3)
(2)
timing.
L
= CE
L
(1,4)
= H, Power-DownMode, I
R/W
X
X
X
L
R
(2)
t
WR
13
(1)
(4)
CE
X
X
L
L
R
(3)
(2)
Right Port
SB1
OE
X
X
X
L
R
or I
SB2
SB3
or I
Industrial and Commercial Temperature Ranges
Function
SB4
A
10R
7FF
7FE
X
X
-A
(4)
0R
INT
H
L
X
X
(2)
(3)
R
Set Right INT
Reset Right INT
Set Left INT
Reset Left INT
Function
L
R
Flag
L
Flag
2654 drw 13
R
Flag
Flag
2654 tbl 13
2654 tbl 14