IDT70121S55J IDT, Integrated Device Technology Inc, IDT70121S55J Datasheet

IC SRAM 18KBIT 55NS 52PLCC

IDT70121S55J

Manufacturer Part Number
IDT70121S55J
Description
IC SRAM 18KBIT 55NS 52PLCC
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT70121S55J

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
18K (2K x 9)
Speed
55ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
52-PLCC
Density
18Kb
Access Time (max)
55ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
22b
Package Type
PLCC
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
240mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
52
Word Size
9b
Number Of Words
2K
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
70121S55J

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT70121S55J
Manufacturer:
IDT
Quantity:
3 000
Part Number:
IDT70121S55J
Manufacturer:
IDT
Quantity:
8 831
Part Number:
IDT70121S55J
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT70121S55J8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Features
Functional Block Diagram
NOTES:
1. 70121 (MASTER): BUSY is non-tri-stated push-pull output.
2. INT is non-tri-stated push-pull output.
©2008 Integrated Device Technology, Inc.
I/O
High-speed access
– Commercial: 25/35/45/55ns (max.)
– Industrial: 35ns (max.)
Low-power operation
– IDT70121/70125S
– IDT70121/70125L
70125 (SLAVE): BUSY is input.
0L
Active: 675mW (typ.)
Standby: 5mW (typ.)
Active: 675mW (typ.)
Standby: 1mW (typ.)
BUSY
- I/O
R/W
INT
A
OE
CE
A
10L
0L
8L
L
L
L
L
L
(1,2)
(2)
Decoder
Address
R/W
OE
CE
L
L
L
HIGH-SPEED
2K x 9 DUAL-PORT
STATIC RAM
WITH BUSY & INTERRUPT
11
Control
I/O
ARBITRATION
INTERRUPT
MEMORY
ARRAY
LOGIC
1
Fully asychronous operation from either port
MASTER IDT70121 easily expands data bus width to 18 bits or
more using SLAVE IDT70125 chip
On-chip port arbitration logic (IDT70121 only)
BUSY output flag on Master; BUSY input on Slave
INT flag for port-to-port communication
Battery backup operation—2V data retention
TTL-compatible, signal 5V (±10%) power supply
Available in 52-pin PLCC
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
Green parts available, see ordering information
Control
I/O
11
Decoder
Address
R/W
CE
OE
R
R
R
OCTOBER 2008
IDT70121S/L
IDT70125S/L
2654 drw 01
OE
CE
R/W
I/O
BUSY
A
A
INT
10R
0R
0R
R
R
R
R
(2)
DSC 2654/11
-I/O
R
(1,2)
8R

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IDT70121S55J Summary of contents

Page 1

... Battery backup operation—2V data retention TTL-compatible, signal 5V (±10%) power supply Available in 52-pin PLCC Industrial temperature range (–40°C to +85°C) is available for selected speeds Green parts available, see ordering information I/O I/O Control Control MEMORY ARRAY 11 11 ARBITRATION INTERRUPT LOGIC 1 IDT70121S/L IDT70125S/L ...

Page 2

... Both devices provide two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power-down Pin Configurations (1,2,3) 05/27/04 ...

Page 3

IDT70121/IDT70125 High-Speed Dual-Port Static RAM with Busy & Interrupt Absolute Maximum Ratings Symbol Rating (2) V Terminal Voltage TERM with Respect to GND T Temperature BIAS Under Bias T Storage STG Temperature I DC Output OUT Current ...

Page 4

IDT70121/IDT70125 High-Speed Dual-Port Static RAM with Busy & Interrupt DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter I Dynamic Operating Current CC (Both Ports Active) I Standby Current SB1 (Both Ports - ...

Page 5

IDT70121/IDT70125 High-Speed Dual-Port Static RAM with Busy & Interrupt Data Retention Characteristics Symbol Parameter V V for Data Retention Data Retention Current CCDR (3) t Chip Deselect to Data Retention Time CDR (3) t ...

Page 6

IDT70121/IDT70125 High-Speed Dual-Port Static RAM with Busy & Interrupt AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Enable Access ...

Page 7

IDT70121/IDT70125 High-Speed Dual-Port Static RAM with Busy & Interrupt Timing Waveform of Read Cycle No. 1, Either Side ADDRESS t OH DATA PREVIOUS DATA VALID OUT BUSY OUT Timing Waveform of Read Cycle No. 2, Either Side ...

Page 8

IDT70121/IDT70125 High-Speed Dual-Port Static RAM with Busy & Interrupt AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol WRITE CYCLE (4) t Write Cycle Time WC t Chip Enable to End-of-Write EW t Address ...

Page 9

IDT70121/IDT70125 High-Speed Dual-Port Static RAM with Busy & Interrupt Timing Waveform of Write Cycle No. 1, R/W Controlled Timing ADDRESS R/W DATA (4) OUT DATA IN Timing Waveform of Write Cycle No. ...

Page 10

IDT70121/IDT70125 High-Speed Dual-Port Static RAM with Busy & Interrupt AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol BUSY TIMING (For MASTER IDT70121) BUSY Access Time from Address t BAA BUSY Disable Time from ...

Page 11

IDT70121/IDT70125 High-Speed Dual-Port Static RAM with Busy & Interrupt Timing Waveform of Write with Port-to-Port Read and BUSY ADDR 'A' R/W 'A' DATA IN'A' (1) t APS ADDR 'B' BUSY 'B' DATA OUT 'B' NOTES ...

Page 12

IDT70121/IDT70125 High-Speed Dual-Port Static RAM with Busy & Interrupt Timing Waveform of BUSY Arbritration Controlled by Address ADDR 'A' ADDRESSES MATCH t (2) APS ADDR 'B' t BUSY 'B' NOTES: 1. All timing is the same for ...

Page 13

... BUSY = V , then No Change BUSY = V , then No Change 'H' = HIGH LOW DON’T CARE ( (2) ( (3) Port Disab le and in Power-Down Mode Power-DownMode (2) Data on Port Written Into Memory IN (3) Data in Memory Output on Port OUT High-Impedance Outputs and t timing. DDD (1,4) Right Port INT Industrial and Commercial Temperature Ranges ...

Page 14

... The message (9 bits) at 7FE or 7FF is user- defined, since addressable SRAM location. If the interrupt function is not used, address locations 7FE and 7FF are not used as mail boxes, but as part of the random access memory. Refer to Table II for the interrupt operation. Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time ...

Page 15

IDT70121/IDT70125 High-Speed Dual-Port Static RAM with Busy & Interrupt Ordering Information XXXXX X XXX Device Power Speed Package Type NOTE: 1. Industrial temperature: for other speeds, packages and powers contact your sales office. Datasheet Document History 01/06/99: ...

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