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PSD834F2-90J
PSD834F2-90J | |
|---|---|
| Manufacturer Part Number | PSD834F2-90J |
| Description | IC FLASH 2MBIT 90NS 52PLCC |
| Manufacturer | STMicroelectronics |
| PSD834F2-90J datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
×
Shipping terms
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Specifications of PSD834F2-90J | |||
|---|---|---|---|
| Format - Memory | FLASH | Memory Type | FLASH |
| Memory Size | 2M (256K x 8) | Speed | 90ns |
| Interface | Parallel | Voltage - Supply | 4.5 V ~ 5.5 V |
| Operating Temperature | 0°C ~ 70°C | Package / Case | 52-PLCC |
| Lead Free Status / RoHS Status | Contains lead / RoHS non-compliant | Other names | 497-2006-5 |
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PSD813F2V, PSD854F2V
Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode
Port Configuration
MCU I/O
Input mode
Valid after internal PSD
PLD Output
configuration bits are
loaded
Address Out
Tri-stated
Data Port
Tri-stated
Peripheral I/O
Tri-stated
Register
PMMR0 and PMMR2
Cleared to '0'
Cleared to '0' by internal
Macrocells flip-flop status
Power-On Reset
Initialized, based on the
1
selection in PSDsoft
VM Register
Configuration menu
All other registers
Cleared to '0'
Note: 1. The SR_cod and PeriphMode bits in the VM Register are always cleared to '0' on Power-On Reset or Warm Reset.
68/109
Power-On Reset
Warm Reset
Input mode
Valid
Tri-stated
Tri-stated
Tri-stated
Power-On Reset
Warm Reset
Unchanged
Depends on .re and .pr
equations
Initialized, based on the
selection in PSDsoft
Configuration menu
Cleared to '0'
Doc ID 10552 Rev 3
Power-down Mode
Unchanged
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Not defined
Tri-stated
Tri-stated
Power-down Mode
Unchanged
Depends on .re and .pr
equations
Unchanged
Unchanged
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