NAND08GAH0FZC5E NUMONYX, NAND08GAH0FZC5E Datasheet
NAND08GAH0FZC5E
Specifications of NAND08GAH0FZC5E
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NAND08GAH0FZC5E Summary of contents
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... Enhanced power saving method by introducing sleep functionality Operating voltage 1.8 V/3 CCQ 1.8 V/3 CCQ 1.8 V/3 CCQ Rev 3 NAND02GRH0L Preliminary Data LFBGA169 LFBGA153 Package Temperature range – -25 to 105 °C LFBGA153 - °C LFBGA169 - °C www.numonyx.com 1/33 1 ...
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... Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 eMMC Standard Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Product specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 System performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Device physical description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 Package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Form factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 Memory array partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 MultiMediaCard interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.2 Bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 6.5 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. LFBGA169 package connections (top view through package Figure 3. LFBGA153 package connections (top view through package Figure 4. Form factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Memory array structure Figure 6. Power- Figure 7. Power cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. LFBGA169 1.4 mm 132+21+16 3R14 - 0.50 mm, package outline . . . . . . . . . . 27 Figure 9. LFBGA153 11 1.3 mm 132 + 21 3R14 - 0.50 mm, package outline . . . . . . . . . . . 29 ...
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... Description 1 Description The NANDxxxxH0x is an embedded flash memory storage solution with MultiMediaCard ™ interface (eMMC communication media. The NANDxxxxH0x is fully compatible with MMC bus and hosts. The NANDxxxxH0x communications are made through an advanced 13-pin bus. The bus can be either 1-bit, 4-bit, or 8-bit in width. The device operates in high-speed mode at clock frequencies equal to or higher than 20 MHz, which is the MMC standard ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 2 Product specification 2.1 System performance Table 2. System performance System performance Multiple block read sequential Multiple block read 64-Kbyte chunk Multiple block write sequential Multiple block write 64-Kbyte chunk 1. Values given for an 8-bit bus ...
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... The controller allows the host to be independent from details of erasing and programming the flash memory. Figure 1. Device block diagram MultiMediaCard interface 8/33 NAND02GRH0L, NAND02GAH0L, NAND08GAH0N diagram. The microcontroller interfaces with a host system allowing Numonyx single chip Control microcontroller Data I/O Flash module AI13614e ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 3.1 Package connections Figure 2. LFBGA169 package connections (top view through package DAT2 ...
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Device physical description Figure 3. LFBGA153 package connections (top view through package DAT0 DAT1 DAT3 DAT4 DAT5 V CCI SSQ ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 3.2 Form factor The ball diameter, d, and the ball pitch, p, for the LFBGA169 and LFBGA153 packages are 0.30 mm (solder ball diameter 0.5 mm (ball pitch) Figure 4. Form factor V ...
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... Write protect group: the smallest unit that may be individually write protected. Its size is defined in units of erase groups. The size of a WP-group depends on each device and is stored in the CSD. Figure 5 shows the NANDxxxxH0x memory array organization. Figure 5. Memory array structure number of last erase group or last write protect group. ...
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... V core supply voltage CC V provides the power supply to the internal core of the memory device the main CC power supply for all operations (read, program and erase). The core voltage (V either within 1.7 V and 1.95 V (NAND02GRH0L) or 2.7 V and 3.6 V (NAND02GAH0L and NAND08GAH0N). ...
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MultiMediaCard interface 5.1.6 V input/output supply voltage CCQ V provides the power supply to the I/O pins and enables all outputs to be powered CCQ independently from V The input/output voltage (V range) or 2.7 V and 3.6 V (high ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 5.2 Bus topology The NANDxxxxH0x device supports the MMC protocol. For more details, refer to section 6.4 of the JEDEC Standard Specification No. JESD84-A43. The section 12 of the JEDEC Standard Specification contains a bus circuitry diagram ...
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... CC 3. Refer to Section 7.1: Operation conditions register (OCR) Figure 7. Power cycling Supply voltage V CCmin V CCQmin Command input prohibited 16/33 NAND02GRH0L, NAND02GAH0L, NAND08GAH0N Memory field working voltage range Control logic working voltage range Supply First CMD1 to card ready ramp- Initialization ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 5.5 Bus operating conditions Refer to section 12.6 of the JEDEC Standard Specification No. JESD84-A43. 5.6 Bus signal levels Refer to section 12.6 of the JEDEC Standard Specification No. JESD84-A43. 5.7 Bus timing Refer to section 12.7 ...
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High speed MultiMediaCard operation 6 High speed MultiMediaCard operation All communication between the host and the device is controlled by the host (master). The following section provides an overview of the identification and data transfer modes, commands, dependencies, various operation ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 6.6 Commands Refer to section 7.9 of the JEDEC Standard Specification No. JESD84-A43. 6.7 State transition Refer to section 7.10 and 7.12 of the JEDEC Standard Specification No. JESD84-A43. 6.8 Response Refer to section 7.11 of the ...
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... Operation conditions register (OCR) The 32-bit operation conditions register stores the V flash memory component. The device is capable of communicating (identification procedure and data transfer) with any MultiMediaCard host using any operating voltage within 1.7 V and 1.95 V (low-voltage range) or 2.7 V and 3.6 V (high-voltage range) depending on the voltage range supported by the host ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 7.2 Card identification (CID) register The CID register is 16-byte long and contains a unique card identification number used during the card identification procedure 128-bit wide register with the content as defined in Table ...
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Device registers Table 8. Card specific data register Name CSD structure MultiMediaCard protocol version Reserved Data read access-time-1 Data read access-time-2 in CLK cycles (NSAC*100) Max. data transfer rate Command classes Max. read data block length Partial blocks for read ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N Table 8. Card specific data register (continued) Name Permanent write protection Temporary write protection File format ECC code 2 R/W/E none 0 CRC Not used, always ‘1’ 7.4 Extended CSD register The extended CSD register defines the ...
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Device registers (1) Table 9. Extended CSD Name Sleep/awake timeout S_A_TIMEOUT (2) Reserved Sector count SEC_COUNT (2) Reserved Minimum write performance for 8 bit at MIN_PERF_W_8_52 52 MHz Minimum read performance for 8 bit at MIN_PERF_R_8_52 52 MHz Minimum write ...
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... Command set revision CMD_SET_REV (2) Reserved Power class POWER_CLASS (2) Reserved High speed interface HS_TIMING timing (2) Reserved Bus width mode BUS_WIDTH (2) Reserved Erased memory content ERASED_MEM_CONT (2) Reserved Boot configuration BOOT_CONFIG (2) Reserved Boot bus width 1 BOOT_BUS_WIDTH (2) Reserved High-density erase group ERASE_GROUP_DEF definition (2) Reserved 1. TBD stands for ‘to be defined’. ...
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Device registers 7.5 RCA (relative card address) register The writable 16-bit relative card address (RCA) register carries the device address assigned by the host during the device identification. This address is used for the addressed host-card communication after the device ...
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... NAND02GRH0L, NAND02GAH0L, NAND08GAH0N 8 Package mechanical To meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which have a lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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Package mechanical Table 10. LFBGA169 1.4 mm 132+21+16 3R14 - 0.50 mm, mechanical data Symbol Typ 1.00 b 0.30 D 12.00 D1 6.50 ddd E 16.00 E1 6.50 E2 10.50 E3 12.50 E4 ...
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NAND02GRH0L, NAND02GAH0L, NAND08GAH0N Figure 9. LFBGA153 11 1.3 mm 132 + 21 3R14 - 0.50 mm, package outline E E1 BALL "A1" Drawing is not to scale Package mechanical ...
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Package mechanical Table 11. LFBGA153 11 1.3 mm 132 + 21 3R14 - 0.50 mm, mechanical data millimeters Symbol Typ A – A1 – A2 1.00 b 0.30 D 11.50 D1 6.50 E 13.00 E1 6.50 e ...
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... Other digits may be added to the ordering code for preprogrammed parts or other options. Devices are shipped from the factory with the memory content bits erased to ’1’. For further information on any aspect of the device, please contact your nearest Numonyx sales office. =1 3.3 V (only for NAND02GRH0L) CCQ = 1 ...
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Revision history 10 Revision history Table 13. Document revision history Date 11-Nov-2008 22-Jan-2009 04-Mar-2009 32/33 NAND02GRH0L, NAND02GAH0L, NAND08GAH0N Revision 1 Initial release. Removed the 4-Gbit density and references to ECOPACK packages 2 throughout the document. LFBGA153 package replaced by LFBGA169. ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...