IDT70T3519S133BC IDT, Integrated Device Technology Inc, IDT70T3519S133BC Datasheet
IDT70T3519S133BC
Specifications of IDT70T3519S133BC
Available stocks
Related parts for IDT70T3519S133BC
IDT70T3519S133BC Summary of contents
Page 1
... Features: True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access – Commercial: 3.4 (200MHz)/3.6ns (166MHz)/ 4.2ns (133MHz)(max.) – Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) Selectable Pipelined or Flow-Through output mode Counter enable and repeat features ...
Page 2
... The IDT70T3519/99/ high-speed 256/128/64K x 36 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times ...
Page 3
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Pin Configuration (3,4,5,6,9) 06/19/ TDI NC (1) A 17L I/O NC TDO NC 18L I/O I/O V ...
Page 4
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Pin Configuration (3,4,5,6,9,10) 06/19/02 1 I/O 19L 2 I/O 19R 3 I/O 20L 4 I/O 20R 5 V DDQL I/O 7 21L 8 I/O 21R 9 I/O ...
Page 5
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Pin Configuration (3,4,5,6,9) 01/23/ I/O I/O V COL TDO 19L 18L I/O V I/O A TDI 20R SS 18R ...
Page 6
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Pin Names Left Port Right Port Chip Enables (Input R/W R/W Read/Write Enable (Input Output Enable ...
Page 7
... Counter Set to last valid ADS load (n) I/O , BEn and OE and BEn , the rising edge of CLK, regardless of all other memory control signals including CE IL 6.42 7 Industrial and Commercial Temperature Ranges (1,2,3,4) Byte 1 Byte 0 I/O I/O MODE 18-26 9-17 0-8 High-Z High-Z Deselected–Power Down ...
Page 8
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Recommended Operating Temperature and Supply Voltage Commercial Industrial NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. Recommended DC Operating Conditions with V Symbol NOTES: ...
Page 9
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Absolute Maximum Ratings Symbol Rating V V Terminal Voltage TERM with Respect to GND DD ( Terminal Voltage TERM DDQ (V ) with Respect to ...
Page 10
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter CE and CE I Dynamic Operating DD L Current (Both Outputs Disabled, (1) Ports Active ...
Page 11
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM AC Test Conditions (V Input Pulse Levels (Address & Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT ∆ tCD ...
Page 12
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) Symbol (1) t Clock Cycle Time (Flow-Through) CYC1 (1) t Clock Cycle Time (Pipelined) CYC2 (1) t ...
Page 13
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Timing Waveform of Read Cycle for Pipelined Operation (1,2) (FT/PIPE = CYC2 t CH2 CLK ...
Page 14
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Timing Waveform of a Multi-Device Pipelined Read t CYC2 t t CH2 CL2 CLK ADDRESS (B1 0(B1) DATA OUT(B1) ...
Page 15
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Timing Waveform of Left Port Write to Pipelined Right Port Read CLK "A" R/W "A" ADDRESS "A" MATCH ...
Page 16
... CNTEN, and REPEAT = Addresses do not have to be accessed sequentially since ADS = V are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled) t CYC2 t CH2 CLK CE ...
Page 17
... Output state (High, Low, or High-impedance) is determined by the previous cycle control signals BEn, and ADS = V , CNTEN, and REPEAT = Addresses do not have to be accessed sequentially since ADS = V reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity ...
Page 18
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Timing Waveform of Pipelined Read with Address Counter Advance t CYC2 t t CH2 CLK ADDRESS SAD HAD ADS CNTEN ( ...
Page 19
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Timing Waveform of Write with Address Counter Advance (Flow-through or Pipelined Inputs) t CYC2 t CH2 CLK ADDRESS (3) INTERNAL An ADDRESS t t SAD ...
Page 20
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Waveform of Interrupt Timing CLK R ADDRESS (3) L 3FFFF ( INS INT ...
Page 21
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Waveform of Collision Timing Both Ports Writing with Left Port Clock Leading CLK L t OFS ( ADDRESS L COL L CLK R t ...
Page 22
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Timing Waveform - Entering Sleep Mode R/W Timing Waveform - Exiting Sleep Mode R/W OE DATA OUT (4) NOTES IH. 2. All timing is same ...
Page 23
... SRAM location. If the interrupt function is not used, address locations 3FFFE and 3FFFF (1FFFF or 1FFFE for IDT70T3599 and FFFF or FFFE for IDT70T3589) are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation. Collision Detection ...
Page 24
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Depth and Width Expansion The IDT70T3519/99/89 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. ...
Page 25
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM JTAG Timing Specifications t JF TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO TRST t JRST NOTES: 1. Device inputs = All device inputs except TDI, TMS, ...
Page 26
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Identification Register Definitions Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) NOTE: 1. Device ID for IDT70T3599 is 0x331. ...
Page 27
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Ordering Information XXXXX A 999 A Device Power Speed Package Type NOTES: 1. 166MHz I-Temp is only available in the BC-256 package. 2. 200Mhz is only available in the BC-256 ...
Page 28
IDT70T3519/99/89S High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM Datasheet Document History: 01/23/03: Initial Datasheet 01/30/03: Page 1 Corrected 208-pin package from TQFP to PQFP 04/25/03: Page 11 Added Capacitance Derating drawing Page 12 Changed t 11/11/03: Page 10 ...