MT28F800B5WP-8 BET Micron Technology Inc, MT28F800B5WP-8 BET Datasheet - Page 7

• Manufacturer Part Number: MT28F800B5WP-8 BET
• Description: IC FLASH 8MBIT 80NS 48TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT28F800B5WP-8 BET

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 8M (1M x 8 or 512K x 16)
• Speed: 80ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FUNCTIONAL DESCRIPTION
ries incorporate a number of features ideally suited for
system firmware. The memory array is segmented into
individual erase blocks. Each block may be erased
without affecting data stored in other blocks. These
memory blocks are read, written and erased with com-
mands to the command execution logic (CEL). The
CEL controls the operation of the internal state
machine (ISM), which completely controls all WRITE,
BLOCK ERASE, and VERIFY operations. The ISM pro-
tects each memory location from over-erasure and
optimizes each memory location for maximum data
retention. In addition, the ISM greatly simplifies the
control necessary for writing the device in-system or in
an external programmer.
mation on the operation of the MT28F800B5 and
MT28F008B5 and is organized into these sections:
OVERVIEW
Smart 5 Technology (B5)
system READ, WRITE and ERASE operations. WRITE
and ERASE operations may be executed with a V
voltage of 3.3V or 5V. Due to process technology
advances, 5V V
duction programming. For any operation, V
Eleven Independently Eraseable
Memory Blocks
into eleven independently erasable memory blocks
that allow portions of the memory to be erased with-
out affecting the rest of the memory data. A special
boot block is hardware-protected against inadvertent
erasure or writing by requiring either a super-voltage
on the RP# pin or driving the WP# pin HIGH. (The WP#
pin does not apply to the SOP package.) One of these
two conditions must exist, along with the V
(5V) on the V
09005aef8075d1ec
MT28F800B5_4.fm - Rev. 4, Pub. 2/2004
The MT28F800B5 and MT28F008B5 Flash memo-
The Functional Description provides detailed infor-
• Overview
• Memory Architecture
• Output (READ) Operations
• Input Operations
• Command Set
• ISM Status Register
• Command Execution
• Error Handling
• WRITE/ERASE Cycle Endurance
• Power Usage
• Power-Up
Smart 5 operation allows maximum flexibility for in-
The MT28F800B5 and MT28F008B5 are organized
PP
PP
pin, before a WRITE or ERASE is per-
is optimal for application and pro-
CC
PP
is at 5V.
voltage
SMART 5 BOOT BLOCK FLASH MEMORY
PP
7
formed on the boot block. The remaining blocks
require that only the V
pin before writing or erasing.
Hardware-Protected Boot Block
written only when the RP# pin is taken to V
the WP# pin is brought HIGH. (The WP# pin does not
apply to the SOP package.) This provides additional
security for the core firmware during in-system firm-
ware updates should an unintentional power fluctua-
tion or system reset occur. The MT28F800B5 and
MT28F008B5 are available with the boot block starting
at the bottom of the address space (“B” suffix) or the
top of the address space (“T” suffix).
Selectable Bus Size (MT28F800B5)
x 8) or 16-bit (512K x 16) data bus for reading and writ-
ing the memory. The BYTE# pin is used to select the
bus width. In the x16 configuration, control data is
read or written only on the lower 8 bits (DQ0–DQ7).
data pins for the selected configuration. When the x8
configuration is selected, data is written in byte form;
when the x16 configuration is selected, data is written
in word form.
Internal State Machine (ISM)
simplified with an ISM that controls all erase and write
algorithms in the memory array. The ISM ensures pro-
tection against over-erasure and optimizes write mar-
gin to each cell.
increments and monitors WRITE attempts, verifies
write margin on each memory cell and updates the
ISM status register. When BLOCK ERASE is performed,
the ISM automatically overwrites the entire addressed
block (eliminates over-erasure), increments and moni-
tors ERASE attempts, and sets bits in the ISM status
register.
ISM Status Register
sor to monitor the status of the ISM during WRITE and
ERASE operations. Two bits of the 8-bit status register
are set and cleared entirely by the ISM. These bits indi-
cate whether the ISM is busy with an ERASE or WRITE
task and when an erase has been suspended. Addi-
This block of the memory array can be erased or
The MT28F800B5 allows selection of an 8-bit (1 Meg
Data written to the memory array utilizes all active
BLOCK ERASE and BYTE/WORD WRITE timing are
During WRITE operations, the ISM automatically
The ISM status register enables an external proces-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PP
voltage be present on the V
©2002 Micron Technology Inc.
HH
8Mb
or when
PP