MT48H4M16LFB4-8 IT Micron Technology Inc, MT48H4M16LFB4-8 IT Datasheet
MT48H4M16LFB4-8 IT
Specifications of MT48H4M16LFB4-8 IT
Related parts for MT48H4M16LFB4-8 IT
MT48H4M16LFB4-8 IT Summary of contents
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SYNCHRONOUS DRAM Features • Temperature compensated self refresh (TCSR) • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 54-Ball FBGA Pin Assignment (Top View ...
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List of Tables Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... The 64Mb SDRAM is designed to operate in 1.8V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, Deep Power- Down Mode. All inputs and outputs are LVTTL-com- patible. SDRAMs offer substantial advances in DRAM oper- ...
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... A0-A11, ADDRESS 14 BA0, BA1 REGISTER pdf: 09005aef80a63953, source: 09005aef808a7edc Y25L_64Mb_2.fm - Rev. E 11/ ROW- BANK0 12 ROW- ADDRESS ADDRESS MUX MEMORY 4096 LATCH & (4,096 x 256 x 16) DECODER SENSE AMPLIFIERS I/O GATING 2 DQM MASK LOGIC BANK READ DATA LATCH CONTROL WRITE DRIVERS LOGIC ...
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... A0–A11) and READ/WRITE command (column-address A0–A7; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1. The address inputs also provide the op-code during a LOAD MODE REGISTER command ...
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Functional Description In general, the 64Mb SDRAMs (1 Meg banks) are quad-bank DRAMs that operate at 1.8V and include a synchronous interface (all signals are regis- tered on the positive edge of the clock signal, CLK). ...
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Table 4: Burst Definition ORDER OF ACCESSES WITHIN STARTING BURST COLUMN TYPE = LENGTH ADDRESS SEQUENTIAL 0-1-2 1-2-3 2-3-0 3-0-1 ...
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CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to one, two, or three clocks. If ...
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... Partial Array Self Refresh For further power savings during SELF REFRESH, the partial array self refresh (PASR) feature allows the controller to select the amount of memory that will be refreshed during SELF REFRESH. The refresh options are all banks (banks and 3); two banks (banks 0 and 1) ...
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Commands Figure 6, Truth Table 1 – Commands and DQM 1 Operation provides a quick reference of available commands. This is followed by a written description of Table 6: Truth Table 1 – Commands and DQM Operation NAME (FUNCTION) COMMAND ...
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... Input data appearing on the DQ is written to the memory array subject to the DQM input logic level appearing coincident with the data given DQM signal is reg- istered LOW, the corresponding data will be written to memory ...
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... REFRESH utilize the row refresh counter. Deep Power-Down The operating mode deep power-down achieves maximum power reduction by eliminating the power of the whole memory array of the device. Array data will not be retained once the device enters deep power-down mode. This mode is entered by having all banks idle then CS# and WE# held low with RAS# and CAS# held high at the rising edge of the clock, while CKE is low ...
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Operation Bank/row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the ...
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READs READ bursts are initiated with a READ command, as shown in Figure 8. The starting column and bank addresses are pro- vided with the READ command, and auto precharge is either enabled or disabled for that burst access. If ...
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Figure 10: Consecutive READ Bursts CLK COMMAND READ NOP NOP NOP READ BANK, BANK, ADDRESS COL n COL OUT OUT CAS Latency = ...
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Figure 12: READ to WRITE CLK DQM COMMAND READ NOP NOP BANK, ADDRESS COL n DQ NOTE: A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE ...
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Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMI- NATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles ...
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Figure 17: WRITE Burst T0 T1 CLK COMMAND WRITE NOP BANK, ADDRESS COL NOTE: Burst length = 2. DQM is LOW. Figure 18: WRITE to WRITE T0 T1 CLK COMMAND ...
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Figure 19: Random WRITE Cycles T0 T1 CLK COMMAND WRITE WRITE BANK, BANK, ADDRESS COL n COL NOTE: Each WRITE command may be to any bank. DQM is LOW. Figure 20: WRITE ...
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... RC Deep power down mode is a maximum power sav- ings feature achieved by shutting off the power to the entire memory array of the device. Data on the mem- T2 ory array will not be retained once deep power down mode is executed. Deep power down mode is entered ...
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DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See examples in Figure 25, Clock ...
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Concurrent Auto Precharge Micron SDRAM devices support Concurrent Auto precharge, which allows an access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing. Four cases where concurrent auto precharge occurs are defined ...
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WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): When a READ to bank m registers, it will interrupt a WRITE on bank n, with the data-out appearing clocks later, (depending on ...
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Table 7: Truth Table 2 – CKE Notes: 1-4: Notes appear below table CKE CKE CURRENT STATE n-1 n Power-Down Self Refresh L L Clock Suspend Deep Power-Down Power-Down Deep Power-Down L H Self Refresh Clock Suspend All Banks Idle ...
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Table 8: Truth Table 3 – Current State Bank n, Command to Bank n Notes: 1-6; notes appear below table CURRENT STATE CS# RAS# CAS# Any Idle ...
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Table 9: Truth Table 4 – Current State Bank n, Command to Bank m Notes: 1-6; notes appear below and on next page CURRENT RAS CAS STATE CS Any Idle X X ...
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READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 12: Electrical Characteristics and Recommended AC Operating Conditions Notes 11; notes appear on page 34 AC CHARACTERISTICS PARAMETER Access time from CLK (pos. edge) Address hold time Address setup time CLK high-level width CLK low-level ...
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Table 13: AC Functional Characteristics Notes 11; notes appear on page 34 PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode ...
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Table 15 Self Refresh Current Options DD Notes: 4; notes appear on page 34; V TEMPERATURE COMPENSATED SELF REFRESH PARAMETER/CONDITION Self Refresh Current: CKE < 0.2V – 4 Banks Open Self Refresh Current: CKE < 0.2V – ...
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Notes 1. All voltages referenced This parameter is sampled 25°C; pin under test biased at 1.4V MHz dependent on output loading and cycle DD rates. Specified values are ...
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Figure 31: Initialize and Load Mode Register CLK ( ( ) ) t t CKS CKH ( ( ) ) CKE ( ( ) ) t t CMS CMH ( ( ) ) 3 COMMAND ...
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T0 CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQML, DQMU A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Two clock cycles Precharge all All banks idle, enter ...
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CLK CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQMU, DQML A0-A9, A11 2 COLUMN A10 ...
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CLK CKE t CKS t CMS COMMAND PRECHARGE DQMU, DQML A0-A9, A11 ALL BANKS A10 SINGLE BANK t AS BA0, BA1 BANK(S) High-Z DQ Precharge all active banks NOTE: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands ...
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T0 CLK CKE t CKS t CMS COMMAND PRECHARGE DQMU, DQML A0-A9, A11 ALL BANKS A10 SINGLE BANK t AS BA0, BA1 BANK(S) High-Z DQ Precharge all active banks NOTE: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back ...
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Figure 36: READ – Without Auto Precharge1 CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 t ...
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Figure 37: READ – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQMU, DQML A0-A9, A11 ROW ROW A10 t AS ...
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Figure 38: Single READ – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 ...
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Figure 39: Single READ – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQMU, DQML A0-A9, A11 ROW ROW A10 t AS ...
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Figure 40: Alternating Bank Read Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 t AS ...
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CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 BA0, BA1 ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 BA0, BA1 BANK DQ ...
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Figure 43: WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 DISABLE ...
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Figure 44: WRITE – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ENABLE AUTO PRECHARGE ...
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Figure 45: Single WRITE – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 ...
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Figure 46: Single WRITE – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH NOP 3 COMMAND ACTIVE DQMU, DQML A0-A9, A11 ROW ...
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Figure 47: Alternating Bank Write Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQMU, DQML COLUMN m 2 A0-A9, A11 ROW t ...
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T0 CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE DQMU, DQML A0-A9, A11 ROW ROW A10 BA0, BA1 BANK DQ t RCD NOTE: 1. ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 BA0, BA1 BANK DQ ...
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Figure 50: 54-Ball FBGA (8mm x 8mm) 0.65 ±0.05 SEATING PLANE C 0.10 C 54X Ø0.45 ±0.05 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS 0.42. BALL A9 6.40 3.20 ±0.05 3.20 ±0.05 8.00 ±0.10 NOTE: ...