MT45W2MW16PGA-70 WT TR Micron Technology Inc, MT45W2MW16PGA-70 WT TR Datasheet - Page 16

• Manufacturer Part Number: MT45W2MW16PGA-70 WT TR
• Description: IC PSRAM 32MBIT 70NS 48VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W2MW16PGA-70 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 32M (2M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 48-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1316-2

Figure 12:
Partial-Array Refresh (CR[2:0]) Default = Full-Array Refresh
Sleep Mode (CR[4]) Default = PAR Enabled, DPD Disabled
PDF: 09005aef82832fa7 / Source: 09005aef82832f97
32mb_asyncpage_cr1_0_p24z_2.fm - Rev. B 5/07 EN
Configuration Register Bit Mapping
The PAR bits restrict REFRESH operation to a portion of the total memory array. This
feature allows the system to reduce current by only refreshing that part of the memory
array required by the host system. The refresh options are full array, one-half array, one-
quarter array, one-eighth array, or none of the array. The mapping of these partitions can
start at either the beginning or the end of the address map (see Table 3 on page 17).
The sleep mode bit determines which low-power mode is to be entered when ZZ# is
driven LOW. If CR[4] = 1, PAR operation is enabled. If CR[4] = 0, DPD operation is
enabled. PAR can also be enabled directly by writing to the CR using the software access
sequence. Note that this then disables ZZ# initiation of PAR. DPD cannot be enabled or
disabled using the software access sequence; this should only be done using ZZ# to
access the CR.
DPD operation disables all refresh-related activity. This mode will be used when the
system does not require the storage provided by the CellularRAM device. Any stored data
will become corrupted when DPD is enabled. When refresh activity has been re-enabled,
the CellularRAM device will require 150µs to perform an initialization procedure before
normal operation can resume. DPD should not be enabled using CR software access.
CR[7]
All must be set to "0"
0
1
Reserved
Page Mode Enable/Disable
Page mode disabled (default)
Page mode enabled
A[20:8]
20–8
32Mb: 2 Meg x 16 Async/Page CellularRAM 1.0 Memory
Page
7
A7
Setting is ignored
CR[4]
(default 00b)
0
1
Ignored
16
6
A6
Sleep Mode
DPD enabled
PAR enabled (default)
A5
5
Sleep
Micron Technology, Inc., reserves the right to change products or specifications without notice.
4
A4
Must be set to "0"
Configuration Register Operation
Reserved
3
A3
CR[2]
2
A2
0
0
0
0
1
1
1
1
CR[1] CR[0]
0
0
1
1
0
0
1
1
PAR
©2007 Micron Technology, Inc. All rights reserved.
1
A1
0
1
0
1
0
1
0
1
PAR Refresh Coverage
Full array (default)
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
None of array
Top 1/2 array
Top 1/4 array
Top 1/8 array
0
A0
Address Bus