CY7C1350B-143AC Cypress Semiconductor Corp, CY7C1350B-143AC Datasheet - Page 3

• Manufacturer Part Number: CY7C1350B-143AC
• Description: IC SRAM 4.5MBIT 143MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1350B-143AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4.5M (128K x 36)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1100

Pin Definitions
Document #: 38-05045 Rev. *A
50–44,
81–82, 99,
100, 32–37
96–93
88
85
89
98
97
92
86
87
29–28,
25–22,
19–18,
13–12, 9–6,
3–2, 79–78,
75–72,
69–68, 63–62
59–56, 53–52
30, 1, 80 51
31
15, 16, 41, 65,
66, 91
4, 11, 14, 20,
27, 54, 61, 70,
77
Pin Number
A
BWS
WE
ADV/LD
CLK
CE
CE
CE
OE
CEN
DQ
DP
MODE
V
V
Name
[16:0]
DD
DDQ
1
2
3
[3:0]
[31:0]
[3:0]
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Input-
Synchronous
I/O-
Synchronous
I/O-
Synchronous
Input Strap pin
Power Supply
I/O Power
Supply
I/O
PRELIMINARY
Address Inputs used to select one of the 131,072 address locations. Sampled at
the rising edge of the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWS
controls DQ
DQ
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new
address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed
to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act
as input data pins. OE is masked during the data portion of a write sequence,
during the first clock when emerging from a deselected state, when the device has
been deselected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recog-
nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN does not deselect the device, CEN can be used to extend the
previous cycle when required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A
read cycle. The direction of the pins is controlled by OE and the internal control
logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQ
three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless
of the state of OE.
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to
DQ
BWS
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. MODE should not change
states during operation. When left floating MODE will default HIGH, to an inter-
leaved burst order.
Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
[31:24]
[31:0]
[31:0]
1
, DP
. During write sequences, DP
are placed in a three-state condition. The outputs are automatically
and DP
2
[15:8]
is controlled by BWS
and DP
3
. See Write Cycle Description table for details.
2
1
1
, and CE
and CE
and CE
1
, BWS
2
3
3
to select/deselect the device.
to select/deselect the device.
to select/deselect the device.
2
2
controls DQ
Description
, and DP
0
[16:0]
is controlled by BWS
during the previous clock rise of the
3
is controlled by BWS
[23:16]
0
controls DQ
and DP
0
2
, DP
, BWS
[7:0]
CY7C1350B
1
and DP
3
is controlled by
.
3
controls
Page 3 of 14
0
, BWS
1