CY7C1350B-143AC Cypress Semiconductor Corp, CY7C1350B-143AC Datasheet - Page 5

• Manufacturer Part Number: CY7C1350B-143AC
• Description: IC SRAM 4.5MBIT 143MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1350B-143AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4.5M (128K x 36)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1100

and DP
tion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1350B has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four WRITE operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial ad-
dress, as described in the Single Write Access section above.
When ADV/LD is driven HIGH on the subsequent clock rise,
the chip enables (CE
nored and the burst counter is incremented. The correct
BWS
in order to write the correct bytes of data.
Interleaved Burst Sequence
Cycle Description Truth Table
Document #: 38-05045 Rev. *A
Ax+1, Ax
00
01
10
11
Deselected
Suspend
Begin Read
Begin Write
Burst Read
Operation
Burst Write
Operation
Notes:
1.
2.
3.
4.
5.
6.
Address
Operation
[3:0]
First
X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWS x = 0 signifies at least one Byte Write Select is active, BWS x =
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
Write is defined by WE and BWS [3:0] . See Write Cycle Description table for details.
The DQ and DP pins are controlled by the current cycle and the OE signal.
CEN=1 inserts wait states.
Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
OE assumed LOW.
[3:0]
inputs must be driven in each cycle of the burst write
are automatically three-stated during the data por-
Ax+1, Ax
01
00
11
10
Address
Second
External
-
External
External
Internal
Internal
1
Address
, CE
Used
2
, and CE
Ax+1, Ax
10
11
00
01
Address
Third
CE
X
X
X
3
1
0
0
) and WE inputs are ig-
[
1, 2, 3, 4, 5, 6
PRELIMINARY
CEN
0
1
0
0
0
0
Ax+1, Ax
11
10
01
00
Address
Fourth
]
ADV/
LD/
X
L
0
0
1
1
WE
X
X
1
X
X
0
Linear Burst Sequence
Ax+1, Ax
00
01
10
11
Address
First
BWS
Valid
Valid
X
X
X
X
x
L-H
L-H
L-H
L-H
L-H
L-H
Ax+1, Ax
01
10
11
00
CLK
Address
Second
I/Os three-state following next rec-
ognized clock.
Clock ignored, all operations sus-
pended.
Address latched.
Address latched, data presented
two valid clocks later.
Burst Read operation. Previous ac-
cess was a Read operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE.
Burst Write operation. Previous ac-
cess was a Write operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE. Bytes written are deter-
mined by BWS
Ax+1, Ax
10
11
00
01
Address
Third
Comments
[3:0]
CY7C1350B
.
Ax+1, Ax
11
00
01
10
Page 5 of 14
Address
Fourth