CY7C1350B-143AC Cypress Semiconductor Corp, CY7C1350B-143AC Datasheet - Page 9

• Manufacturer Part Number: CY7C1350B-143AC
• Description: IC SRAM 4.5MBIT 143MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1350B-143AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4.5M (128K x 36)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1100

Switching Characteristics
Document #: 38-05045 Rev. *A
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Shaded areas contain advanced information.
Notes:
15. t
16. At any given voltage and temperature, t
17. This parameter is sampled and not 100% tested.
CYC
CH
CL
AS
AH
CO
DOH
CENS
CENH
WES
WEH
ALS
ALH
DS
DH
CES
CEH
CHZ
CLZ
EOHZ
EOLZ
EOV
voltage.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
CHZ
, t
CLZ
, t
Clock Cycle Time
Clock HIGH
Clock LOW
Address Set-Up Before CLK
Rise
Address Hold After CLK Rise
Data Output Valid After CLK
Rise
Data Output Hold After CLK
Rise
CEN Set-Up Before CLK Rise
CEN Hold After CLK Rise
GW, BWS
CLK Rise
GW, BWS
Rise
ADV/LD Set-Up Before CLK
Rise
ADV/LD Hold after CLK Rise
Data Input Set-Up Before CLK
Rise
Data Input Hold After CLK Rise 0.5
Chip Enable Set-Up Before
CLK Rise
Chip Enable Hold After CLK
Rise
Clock to High-Z
Clock to Low-Z
OE HIGH to Output High-Z
15, 16, 17]
OE LOW to Output Low-Z
15, 16, 17]
OE LOW to Output Valid
OEV
, t
EOLZ
, and t
Description
[3:0]
[3:0]
EOHZ
Set-Up Before
Hold After CLK
[12, 15, 16, 17]
[12, 15, 16, 17]
are specified with A/C test conditions shown in part (a) of AC Test Loads. Transition is measured 200 mV from steady-state
Over the Operating Range
EOHZ
[15]
[12,
PRELIMINARY
is less than t
[12,
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
5.0
1.4
1.4
1.5
0.5
1.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
1.5
0.5
1.5
1.5
0.0
-166
EOLZ
3.5
3.2
3.0
3.2
and t
CHZ
6.6
2.5
2.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
1.5
0
is less than t
[14, 15, 16]
-150
3.8
3.2
3.0
3.5
CLZ
7.0
2.8
2.8
2.0
0.5
1.5
2.0
0.5
2.0
0.5
2.0
0.5
1.7
0.5
2.0
0.5
1.5
1.5
0
to eliminate bus contention between SRAMs when sharing the same
-143
4.0
3.5
4.0
4.0
7.5
3.0
3.0
2.0
0.5
1.5
2.0
0.5
2.0
0.5
2.0
0.5
1.7
0.5
2.0
0.5
1.5
1.5
0
-133
4.2
3.5
4.2
4.2
4.0
4.0
2.2
0.5
1.5
2.2
0.5
2.2
0.5
2.2
0.5
2.0
0.5
2.2
0.5
1.5
1.5
10
0
-100
5.0
3.5
5.0
5.0
CY7C1350B
12.5
4.0
4.0
2.5
1.0
1.5
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
1.5
1.5
0
-80
Page 9 of 14
7.0
5.0
7.0
7.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns