M48Z35AV-10MH1E STMicroelectronics, M48Z35AV-10MH1E Datasheet - Page 11

• Manufacturer Part Number: M48Z35AV-10MH1E
• Description: IC NVSRAM 256KBIT 100NS 28SOIC
• Manufacturer: STMicroelectronics

Specifications of M48Z35AV-10MH1E

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 256K (32K x 8)
• Speed: 100ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC, 28-SOH (8.48mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2880-5; M48Z35AV-10MH1

M48Z35AV
2.3
Note:
Table 4.
1. Valid for ambient operating temperature: T
2. C
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Data retention mode
With valid V
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V
become high impedance, and all inputs are treated as “Don't care.”
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
user can be assured the memory will be in a write protected state, provided the V
is not less than t
into the deselect window during the time the device is sampling V
of the power supply lines is recommended.
When V
preserves data. The internal button cell will maintain data in the M48Z35AV for an
accumulated period of at least 10 years (at 25°C) when V
As system power returns and V
power supply is switched to external V
V
V
PFD
PFD
t
t
WHQX
WLQZ
Symbol
L
(min) plus t
(max).
t
t
t
t
t
t
t
t
t
t
t
t
= 5 pF (see
t
WLWH
WHDX
WHAX
DVWH
AVWH
AVWL
EHAX
DVEH
EHDX
ELEH
AVEH
AVAV
AVEL
CC
(2)(3)
(2)(3)
drops below V
CC
WRITE mode AC characteristics
applied, the M48Z35AV operates as a conventional BYTEWIDE™ static
Figure 10 on page
F
REC
WRITE cycle time
Address valid to WRITE enable low
Address valid to chip enable low
WRITE enable pulse width
Chip enable low to chip enable high
WRITE enable high to address transition
Chip enable high to address transition
Input valid to WRITE enable high
Input valid to chip enable high
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
Address valid to WRITE enable high
Address valid to chip enable high
WRITE enable high to output transition
. The M48Z35AV may respond to transient noise spikes on V
(min). Normal RAM operation can resume t
CC
SO
falls within the V
, the control circuit switches power to the internal battery which
15).
Doc ID 6784 Rev 8
CC
Parameter
rises above V
A
CC
= 0 to 70 °C; V
. Write protection continues until V
(1)
PFD
(max), V
SO
CC
, the battery is disconnected, and the
= 3.0 to 3.6 V (except where noted).
PFD
CC
(min) window. All outputs
is less than V
REC
Min
100
10
CC
80
80
10
10
50
50
80
80
0
0
5
5
M48Z35AV
. Therefore, decoupling
after V
–100
Operating modes
SO
PFD
CC
Max
CC
50
.
exceeds
CC
(min), the
reaches
CC
that reach
fall time
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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