W25X32VSFIG

Manufacturer Part NumberW25X32VSFIG
DescriptionIC FLASH 32MBIT 75MHZ 16SOIC
ManufacturerWinbond Electronics
W25X32VSFIG datasheet
 

Specifications of W25X32VSFIG

Format - MemoryFLASHMemory TypeFLASH
Memory Size32M (4M x 8)Speed75MHz
InterfaceSPI SerialVoltage - Supply2.7 V ~ 3.6 V
Operating Temperature-40°C ~ 85°CPackage / Case16-SOIC
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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W25X16, W25X32, W25X64
16M-BIT, 32M-BIT, AND 64M-BIT
SERIAL FLASH MEMORY WITH
4KB SECTORS AND DUAL OUTPUT SPI
Publication Release Date:
- 1 -
March 21, 2007, Revision F

W25X32VSFIG Summary of contents

  • Page 1

    ... AND 64M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL OUTPUT SPI W25X16, W25X32, W25X64 Publication Release Date March 21, 2007, Revision F ...

  • Page 2

    ... Block Protect Bits (BP2, BP1, BP0)..............................................................................12 11.1.4 Top/Bottom Block Protect (TB).....................................................................................12 11.1.5 Reserved Bits ...............................................................................................................12 11.1.6 Status Register Protect (SRP) ......................................................................................13 11.1.7 Status Register Memory Protection ..............................................................................14 11.2 INSTRUCTIONS........................................................................................................... 16 11.2.1 Manufacturer and Device Identification.........................................................................16 11.2.2 Instruction Set...............................................................................................................17 11.2.3 Write Ensable (06h)......................................................................................................18 W25X16, W25X32, W25X64 ...

  • Page 3

    Write Disable (04h).......................................................................................................18 11.2.5 Read Status Register (05h) ..........................................................................................19 11.2.6 Write Status Register (01h) ..........................................................................................20 11.2.7 Read Data (03h) ...........................................................................................................21 11.2.8 Fast Read (0Bh) ...........................................................................................................22 11.2.9 Fast Read Dual Output (3Bh) .......................................................................................23 11.2.10 Page Program (02h) ...................................................................................................24 11.2.11 Sector ...

  • Page 4

    ... Single 2.7 to 3.6V supply – 5mA active current, 1µA Power-down (typ) – -40° to +85°C operating range • Software and Hardware Write Protection – Write-Protect all or portion of memory – Enable/Disable protection with /WP pin – Top or bottom array protection • Space Efficient Packaging – ...

  • Page 5

    PIN CONFIGURATION SOIC 208-MIL Figure 1a. W25X16 and W25X32 Pin Assignments, 8-pin SOIC (Package Code SS) 4. PAD CONFIGURATION WSON 6X5-MM Figure 1b. W25X16 Pad Assignments, 8-pad WSON (Package Code ZP) W25X16, W25X32, W25X64 Publication Release Date ...

  • Page 6

    PIN CONFIGURATION PDIP 300-MIL Figure 1c. W25X16, W25X32, W25X64 Pin Assignments, 8-pin PDIP (Package Code DA) 6. PIN DESCRIPTION SOIC 208-MIL, PDIP 300-MIL, AND WSON 6X5-MM PIN NO. PIN NAME 1 / /WP 4 GND 5 ...

  • Page 7

    PIN CONFIGURATION SOIC 300-MIL Figure 1d. W25X16, W25X32 and W25X64 Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) 8. PIN DESCRIPTION SOIC 300-MIL PIN NO. PIN NAME 1 /HOLD 2 VCC 3 N/C 4 N/C 5 N/C 6 N/C ...

  • Page 8

    ... The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (BP2, BP1, and BP0) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The /WP pin is active low. ...

  • Page 9

    BLOCK DIAGRAM /WP /HOLD CLK /CS DIO DO Figure 2. W25X16, W25X32 and W25X64 Block Diagram W25X16, W25X32, W25X64 7FFF00h 7FFFFFh 7F0000h 7F00FFh 40FF00h 40FFFFh 400000h 4000FFh 3FFF00h 3FFFFFh 3F0000h 3F00FFh 20FF00h 20FFFFh 200000h 2000FFh 1FFF00h 1FFFFFh 1F0000h 1F00FFh ...

  • Page 10

    ... The W25X16/32/64 supports Dual output operation when using the "Fast Read with Dual Output" (3B hex) instruction. This feature allows data to be transferred from the Serial Flash memory at twice the rate possible with the standard SPI. This instruction is ideal for quickly downloading code from Flash to RAM upon power-up (code-shadowing) or for applications that cache code-segments to RAM for execution ...

  • Page 11

    ... Status Register Protect (SRP) and Block Protect (TB, BP2, BP1, and BP0) bits. These Status Register bits allow a portion or all of the memory to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control ...

  • Page 12

    ... CONTROL AND STATUS REGISTERS The Read Status Register instruction can be used to provide status on the availability of the Flash memory array, if the device is write enabled or disabled, and the state of write protection. The Write Status Register instruction can be used to configure the devices write protection features. See Figure 3. ...

  • Page 13

    Status Register Protect (SRP) The Status Register Protect (SRP) bit is a non-volatile read/write bit in status register (S7) that can be used in conjunction with the Write Protect (/WP) pin to disable writes to status register. When the ...

  • Page 14

    ... Status Register Memory Protection (1) STATUS REGISTER TB BP2 BP1 BP0 BLOCK( 126 and 127 124 and 127 120 thru 127 112 thru 127 thru 127 thru 127 thru 127 (1) STATUS REGISTER TB BP2 BP1 BP0 BLOCK( thru thru thru thru W25X16, W25X32, W25X64 ...

  • Page 15

    ... Note don’t care W25X16, W25X32, W25X64 W25X16 (16M-BIT) MEMORY PROTECTION ADDRESSES NONE NONE 31 1F0000h - 1FFFFFh 1E0000h - 1FFFFFh 1C0000h - 1FFFFFh 180000h - 1FFFFFh 100000h - 1FFFFFh 0 000000h - 00FFFFh 0 and 1 000000h - 01FFFFh 0 thru 3 000000h - 03FFFFh 0 thru 7 000000h - 07FFFFh 000000h - 0FFFFFh 000000h - 1FFFFFh ...

  • Page 16

    ... Write, Program or Erase must complete on a byte boundary (CS driven high after a full 8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status Register is being written, all instructions except for Read Status Register will be ignored until the program or erase cycle has completed ...

  • Page 17

    ... A15–A8 A7–A0 dummy A15–A8 A7–A0 (D7–D0) A15–A8 A7–A0 A15–A8 A7–A0 dummy dummy (ID7-ID0) dummy 00h (M7-M0) (ID15-ID8) (ID7-ID0) Memory Capacity Type - 17 - BYTE 6 N-BYTES (2) (Next byte) continuous (Next Byte) (D7–D0) continuous I/O = (one byte (D6,D4,D2,D0) per 4 clocks continuous) ...

  • Page 18

    Write Enable (06h) The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip ...

  • Page 19

    Read Status Register (05h) The Read Status Register instruction allows the 8-bit Status Register to be read. The instruction is entered by driving /CS low and shifting the instruction code “05h” into the DIO pin on the rising edge ...

  • Page 20

    ... The Write Status Register instruction allows the Block Protect bits (TB, BP2, BP1 and BP0 set for protecting all, a portion, or none of the memory from erase and program instructions. Protected areas become read-only (see Status Register Memory Protection table). The Write Status Register instruction also allows the Status Register Protect bit (SRP set ...

  • Page 21

    ... DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock continues. The instruction is completed by driving /CS high. The Read Data instruction sequence is shown in figure 8 ...

  • Page 22

    Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of F eight “dummy” clocks after the 24-bit address as shown in figure 9. The ...

  • Page 23

    Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins, DO and DIO, instead of just DO. This allows data ...

  • Page 24

    ... Page Program (02h) The Page Program instruction allows up to 256 bytes of data to be programmed at previously erased to all 1s (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “ ...

  • Page 25

    ... Sector Erase (20h) The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...

  • Page 26

    ... Block Erase (D8h) The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...

  • Page 27

    ... Chip Erase (C7h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “ ...

  • Page 28

    Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ...

  • Page 29

    Release Power-down / Device ID (ABh) The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state, obtain the devices electronic identification (ID) number or do ...

  • Page 30

    Figure 17. Release Power-down / Device ID Instruction Sequence Diagram - 30 - W25X16, W25X32, W25X64 ...

  • Page 31

    Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/Device ...

  • Page 32

    ... JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure 19. For memory type and capacity values refer to Manufacturer and Device Identification table. ...

  • Page 33

    ELECTRICAL CHARACTERISTICS 12.1 Absolute Maximum Ratings PARAMETERS Supply Voltage Voltage applied to any Pin Transient Voltage on any Pin Storage Temperature Lead Temperature Electrostatic Discharge Voltage Notes: 1. Specifications for W25X32 and W25X64 are preliminary. See preliminary designation at ...

  • Page 34

    Endurance and Data Retention PARAMETER Erase/Program Cycles 4KB sector, 64KB block or full chip. Data Retention 55°C 12.4 Power-up Timing and Write Inhibit Threshold PARAMETER VCC (min) to /CS Low Time Delay Before Write Instruction Write Inhibit Threshold Voltage ...

  • Page 35

    DC Electrical Characteristics PARAMETER SYMBOL Input Capacitance C (1) IN Output Capacitance Cout (1) Input Leakage I LI I/O Leakage I LO Standby Current Power-down Current Current Read Data / Dual Output Read ...

  • Page 36

    AC Measurement Conditions PARAMETER Load Capacitance Load Capacitance for FR only 1 Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages Note: 1. Output Hi-Z is defined as the point where data ...

  • Page 37

    AC Electrical Characteristics DESCRIPTION Clock frequency for all instructions, except Read Data (03h) 2.7V-3.6V VCC & Industrial Temperature Clock frequency for all instructions, except Read Data (03h) 3.0V-3.6V VCC & Commercial Temperature Clock frequency, for Fast Read (0Bh, 3Bh) ...

  • Page 38

    AC Electrical Characteristics ( DESCRIPTION /HOLD Active Setup Time relative to CLK /HOLD Active Hold Time relative to CLK /HOLD Not Active Setup Time relative to CLK /HOLD Not Active Hold Time relative to CLK /HOLD to Output Low-Z ...

  • Page 39

    Serial Output Timing 12.10 Input Timing 12.11 Hold Timing W25X16, W25X32, W25X64 Publication Release Date March 21, 2007, Revision F ...

  • Page 40

    PACKAGE SPECIFICATION 13.1 8-Pin SOIC 208-mil (Package Code SS) SYMBOL θ y Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. ...

  • Page 41

    PDIP 300-mil (Package Code DA Symbol α ...

  • Page 42

    WSON W25X16, W25X32, W25X64 - 42 - ...

  • Page 43

    WSON Cont’d. W25X16, W25X32, W25X64 Publication Release Date March 21, 2007, Revision F ...

  • Page 44

    SOIC 300-mil (Winbond Package Code SF) SYMBOL ( ( θ y Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. ...

  • Page 45

    ORDERING INFORMATION Notes: nd 1a. Only the 2 letter is used for the part marking. 1b. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T), when placing orders. ...

  • Page 46

    ... ZP 16M-bit WSON-8 6x5mm 32M-bit ZE WSON-8 8x6mm 64M-bit 16M-bit DA 32M-bit PDIP-8 300mil 64M-bit W25X16, W25X32, W25X64 PRODUCT NUMBER W25X16VSSIG W25X32VSSIG W25X16VSFIG W25X32VSFIG W25X64VSFIG W25X16VZPIG W25X32VZEIG W25X64VZEIG W25X16VDAIZ W25X32VDAIZ W25X64VDAIZ - 46 - TOP SIDE MARKING 25X16VSIG 25X32VSIG 25X16VFIG 25X32VFIG 25X64VFIG 25X16VPIG 25X32VEIG 25X64VEIG 25X16VAIZ ...

  • Page 47

    REVISION HISTORY VERSION DATE A 02/13/06 B 06/28/06 C 10/19/06 D 2/1/07 E 2/26/07 F 3/21/07 W25X16, W25X32, W25X64 PAGE New Create Added W25X64 in the product family. Added 300mil PDIP package. Added 6x5 mm WSON package. Updated Endurance ...

  • Page 48

    ... The specifications are subject to change and are not g authorized sales representative should be consulted for current information before using this product. Trademarks Winbond and spiFlash are trademarks of Winbond Electronics Corporation. All other marks are the property of their respective owner. Important Notice ...