PCF85134HL/1,118 NXP Semiconductors, PCF85134HL/1,118 Datasheet
PCF85134HL/1,118
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PCF85134HL/1,118 Summary of contents
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PCF85134 Universal LCD driver for low multiplex rates Rev. 01 — 17 December 2009 1. General description The PCF85134 is a peripheral device which interfaces to almost any LCD multiplex rates. It generates the drive signals for any static or ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Name PCF85134HL/1 LQFP80 4. Marking Table 2. Type number PCF85134HL/1 PCF85134_1 Product data sheet Description plastic low profile quad flat package; 80 leads; body 12 12 1.4 mm Marking codes Rev. 01 — 17 December 2009 PCF85134 ...
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... NXP Semiconductors 5. Block diagram V LCD LCD BIAS GENERATOR V SS CLK CLOCK SELECT AND TIMING SYNC OSC OSCILLATOR SCL INPUT FILTERS SDA Fig 1. Block diagram of PCF85134 PCF85134_1 Product data sheet BP0 BP1 BP2 BP3 BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR DISPLAY CONTROL PCF85134 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 Fig 2. PCF85134_1 Product data sheet PCF85134 Top view. For mechanical details, see Figure Pin configuration for SOT315-1 (PCF85134) Rev. 01 — ...
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... NXP Semiconductors 6.2 Pin description Table 3. Symbol S31 to S59 BP0 to BP3 n.c. SDA SCL CLK V DD SYNC OSC SA0 LCD S0 to S30 PCF85134_1 Product data sheet Pin description Pin Description LCD segment output LCD backplane output not connected C-bus serial data input and output ...
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... NXP Semiconductors 7. Functional description The PCF85134 is a versatile peripheral device designed to interface any microprocessor or microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and segments. The display configurations possible with the PCF85134 depend on the number of active backplane outputs required. A selection of display confi ...
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... NXP Semiconductors • The I • The data pointer and the subaddress counter are cleared (set to logic 0) • The display is disabled Remark: Do not transfer data on the I reset action to complete. 7.2 LCD bias generator Fractional LCD biasing voltages are obtained from an internal voltage divider of three ...
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... NXP Semiconductors where the values for n are for static drive mode for 1:2 multiplex drive mode for 1:3 multiplex drive mode for 1:4 multiplex drive mode The RMS off-state voltage (V V off RMS Discrimination is the ratio ----------------------- - V off RMS Using Equation 1 bias is ...
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... NXP Semiconductors 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Fig 4. PCF85134_1 Product data sheet V LCD BP0 V SS ...
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... NXP Semiconductors 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF85134 allows the use of Figure 6. Fig 5. PCF85134_1 Product data sheet 1 1 bias LCD V /2 BP0 LCD LCD BP1 V /2 LCD V SS ...
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... NXP Semiconductors Fig 6. PCF85134_1 Product data sheet V LCD 2V /3 LCD BP0 V /3 LCD LCD 2V /3 LCD BP1 V /3 LCD LCD 2V /3 LCD LCD LCD 2V /3 LCD S n LCD LCD 2V /3 LCD V /3 LCD state LCD 2V /3 LCD V LCD V LCD 2V /3 LCD ...
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... NXP Semiconductors 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as shown in Fig 7. PCF85134_1 Product data sheet Figure 7. V LCD 2V /3 LCD BP0 V /3 LCD LCD 2V /3 LCD BP1 V /3 LCD V SS ...
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... NXP Semiconductors 7.4.4 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in BP0 BP1 BP2 BP3 Sn Sn+1 Sn+2 Sn+3 state 1 state 2 Fig 8. PCF85134_1 Product data sheet Figure 8. V LCD 2V /3 LCD V /3 LCD ...
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... NXP Semiconductors 7.5 Oscillator The internal logic and the LCD drive signals of the PCF85134 are timed by the frequency f , which equals either the built-in oscillator frequency f clk f . The clock frequency f clk(ext) 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to pin V output from pin CLK is the clock signal for any cascaded PCF85134 in the system ...
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... NXP Semiconductors 7.9 Backplane outputs The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane output signals are generated based on the selected LCD drive mode. • In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD. If less than four backplane outputs are required the unused outputs can be left open-circuit. • ...
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LCD segments LCD backplanes S a n+2 BP0 n+3 n+1 static n+5 n n+6 BP0 1 ...
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... NXP Semiconductors The following applies to • In static drive mode the eight transmitted data bits are placed into row 0 of eight successive 4-bit RAM words. • In 1:2 multiplex mode the eight transmitted data bits are placed in pairs into row 0 and 1 of four successive 4-bit RAM words. ...
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... NXP Semiconductors Once the display RAM of the first PCF85134 has been written, the second PCF85134 is selected by sending the device-select command again. This time however the command matches the second device's hardware subaddress. Next the load-data-pointer command is sent to select the preferred display RAM address of the second PCF85134. ...
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... NXP Semiconductors Table 7. Blink mode off additional feature is for an arbitrary selection of LCD segments to blink. This applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. By means of the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blink frequency. This mode can also be specifi ...
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... NXP Semiconductors 8. Basic architecture 8.1 Characteristics of the I 2 The I C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...
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... NXP Semiconductors SDA SCL Fig 13. System configuration 8.1.3 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. • ...
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... NXP Semiconductors 2 8.1.4 I C-bus controller The PCF85134 acts transmit data the acknowledge signals of the selected devices. Device selection depends on the 2 I C-bus slave address, the transferred command data and the hardware subaddress. In single device applications, the hardware subaddress inputs A0, A1, and A2 are ...
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... NXP Semiconductors R slave address control byte EXAMPLES a) transmit two bytes of RAM data transmit two command bytes transmit one command byte and two RAM date bytes Fig 15. I C-bus protocol After acknowledgement, the control byte is sent defining if the next byte is a RAM or command information. The control byte also defi ...
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... NXP Semiconductors The acknowledgement after each byte is made only by the (A0, A1, and A2) addressed PCF85134. After the last display byte, the I Alternatively a START may be issued to RESTART I 8.3 Command decoder The command decoder identifies command bytes that arrive on the I five commands: Table 9. ...
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... NXP Semiconductors Table 13. See Section Bit [1] The bank-select command has no effect in 1:3 or 1:4 multiplex drive modes. Table 14. See Section Bit [1] Normal blinking can only be selected in multiplex drive mode 1:3 or 1:4. [2] For the blink frequencies, see 8.4 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers of the PCF85134 and coordinates their effects ...
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... NXP Semiconductors 9. Internal circuitry Fig 17. Device protection diagram PCF85134_1 Product data sheet Universal LCD driver for low multiplex rates V DD SA0 CLK OSC SYNC A0, A1 LCD BP0, BP1, BP2, BP3 LCD S0 to S59 V SS Rev. 01 — 17 December 2009 PCF85134 SCL V SS ...
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... NXP Semiconductors 10. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (V LCD display artifacts. To avoid such artifacts, V Table 15. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol LCD I DD(LCD tot P/out ...
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... NXP Semiconductors 11. Static characteristics Table 16. Static characteristics Symbol Parameter Supplies V supply voltage DD V LCD supply voltage LCD I supply current DD I LCD supply current DD(LCD) Logic V input voltage I V LOW-level input voltage IL V HIGH-level input voltage IH V power-on reset voltage POR I LOW-level output current output sink current ...
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... NXP Semiconductors 12. Dynamic characteristics Table 17. Dynamic characteristics Symbol Parameter Clock Internal: output pin CLK f oscillator frequency osc External: input pin CLK f external clock frequency clk(ext) t HIGH-level clock time clk(H) t LOW-level clock time clk(L) Synchronization: input pin SYNC t SYNC propagation delay ...
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... NXP Semiconductors BP0 to BP3, and S0 to S59 Fig 18. Driver timing waveforms SDA SCL SDA Fig 19. I PCF85134_1 Product data sheet clk t clk(H) CLK SYNC t PD(SYNC_N BUF LOW t HD;STA C-bus timing waveforms Rev. 01 — 17 December 2009 PCF85134 Universal LCD driver for low multiplex rates ...
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... NXP Semiconductors 13. Application information 13.1 Cascaded operation Large display configurations PCF85134 can be recognized on the same 2 I C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable 2 I C-bus slave address (SA0). Table 18. Cluster 1 2 When cascaded PCF85134 are synchronized, they can share the backplane signals from one of the devices in the cascade ...
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... NXP Semiconductors V LCD V DD HOST MICRO- PROCESSOR/ MICRO- CONTROLLER V SS Fig 20. Cascaded PCF85134 configuration The SYNC line is provided to maintain the correct synchronization between all cascaded PCF85134. Synchronization is guaranteed after a power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments or by defi ...
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... NXP Semiconductors Fig 21. Synchronization of the cascade for various PCF85134 drive modes The contact resistance between the SYNC pins of cascaded devices must be controlled. If the resistance is too high, the device will not be able to synchronize properly. Table 19 Table 19. Number of devices PCF85134_1 Product data sheet ...
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... NXP Semiconductors 14. Package outline LQFP80: plastic low profile quad flat package; 80 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.16 1.5 mm 1.6 0.25 0.04 1.3 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors 15. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A , IEC 61340-5 or equivalent standards. 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors 16.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16.4 Refl ...
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... NXP Semiconductors Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 17. Abbreviations Table 22. Acronym CMOS ESD HBM IC LCD MM RAM PCF85134_1 Product data sheet maximum peak temperature ...
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... NXP Semiconductors 18. References [1] AN10365 — Surface mount reflow soldering description [2] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [4] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Power-On Reset (POR 7.2 LCD bias generator 7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 7 7.4 LCD drive mode waveforms . . . . . . . . . . . . . . . 9 7 ...