PCA85176T/Q900/1,1 NXP Semiconductors, PCA85176T/Q900/1,1 Datasheet - Page 32

IC LCD DRIVER 40SEG 56TSSOP

PCA85176T/Q900/1,1

Manufacturer Part Number
PCA85176T/Q900/1,1
Description
IC LCD DRIVER 40SEG 56TSSOP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA85176T/Q900/1,1

Package / Case
56-TSSOP
Display Type
LCD
Configuration
40 Segment
Interface
I²C
Current - Supply
80µA
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 95°C
Mounting Type
Surface Mount
Number Of Digits
20
Number Of Segments
40
Maximum Clock Frequency
4800 Hz
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Power Dissipation
400 mW
Maximum Operating Temperature
+ 95 C
Attached Touch Screen
No
Maximum Supply Current
20 uA
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Digits Or Characters
-
Lead Free Status / Rohs Status
 Details
Other names
568-5109-2
NXP Semiconductors
PCA85176_1
Product data sheet
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCA85176. Synchronization is guaranteed after a power-on reset. The only time that
SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments or by defining a multiplex drive mode when PCA85176
with different SA0 levels are cascaded).
SYNC is organized as an input/output pin. The output selection is realized as an
open-drain driver with an internal pull-up resistor. A PCA85176 asserts the SYNC line at
the onset of its last active backplane signal and monitors the SYNC line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCA85176 to assert
SYNC. The timing relationship between the backplane waveforms and the SYNC signal
for the various drive modes of the PCA85176 are shown in
The contact resistance between the SYNC on each cascaded device must be controlled.
If the resistance is too high, the device is not able to synchronize properly; this is
particularly applicable to chip-on-glass applications. The maximum SYNC contact
resistance allowed for the number of devices in cascade is given in
Fig 23. Cascaded PCA85176 configuration
V
V
V
SS
DD
CONTROLLER
PROCESSOR/
LCD
(1) Is master (OSC connected to V
(2) Is slave (OSC connected to V
MICRO-
MICRO-
HOST
R
All information provided in this document is subject to legal disclaimers.
2C
t
r
b
Rev. 01 — 14 April 2010
DD
SS
).
SYNC
SYNC
).
OSC
SDA
SCL
CLK
OSC
SDA
CLK
SCL
A0
Universal LCD driver for low multiplex rates
A0
A1
PCA85176
PCA85176
V DD
V
A1
DD
A2
(1)
(2)
A2 SA0
V LCD
SA0
V
LCD
V
SS
V
Figure
SS
40 segment drives
40 segment drives
4 backplanes
BP0 to BP3
BP0 to BP3
(open-circuit)
24.
PCA85176
Table
© NXP B.V. 2010. All rights reserved.
19.
LCD PANEL
013aaa052
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