LTC4257IS8 Linear Technology, LTC4257IS8 Datasheet - Page 15

• Manufacturer Part Number: LTC4257IS8
• Description: IC CONTROLLER POE INTERFAC 8SOIC
• Manufacturer: Linear Technology
• Type: Power over Ethernet Switch (PoE)r

Specifications of LTC4257IS8

• Applications: IP Phones, Power over LAN, Network Routers and Switches
• Internal Switch(s): Yes
• Current Limit: 350mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
Classification Resistor Selection (R
IEEE 802.3af allows classifying PDs into four distinct
classes with class 4 being reserved for future use (Table 2).
An external resistor connected from R
ure 3) sets the value of the classification current. The
designer should determine which power category the PD
falls into and then select the appropriate value of R
from Table 2. If a unique classification current is required,
the value of R
where I
classification and is given in the electrical specifications.
The R
degrading the overall accuracy of the classification cir-
cuit. Resistor power dissipation will be 50mW maximum
and is transient so heating is typically not a concern. In
order to maintain loop stability, the layout should
minimize capacitance at the R
tion circuit can be disabled by floating the R
R
CLASS
CLASS
IN_CLASS
= 1.237V/(I
resistor must be 1% or better to avoid
CLASS
is the LTC4257 IC supply current during
U
can be calculated as:
PSE
PSE
TO
TO
DESIRED
–48V
–48V
U
4
4
CLASS
– I
V
V
IN
IN
IN_CLASS
LTC4257
LTC4257
W
PWRGD
PWRGD
node. The classifica-
V
CLASS
V
GND
GND
OUT
OUT
ACTIVE-HIGH ENABLE FOR RUN PIN WITH INTERNAL PULLUP
CLASS
Figure 10. Power Good Interface Examples
)
ACTIVE-LOW ENABLE, 5.1V SWING
8
6
8
6
5
5
*C15 OPTIONAL TO FILTER PWRGD.
*C15 AND C17 OPTIONAL TO FILTER PWRGD.
SEE APPLICATIONS INFORMATION
SEE APPLICATIONS INFORMATION
+
+
)
CLASS
to V
U
C1
5µF
100V
C1
5µF
100V
pin. The
IN
CLASS
(Fig-
R9
100k
R9
100k
R18
R18
10k
10k
D6
MMBD4148
D6
5.1V
MMBZ5231B
R
force the LTC4257 classification circuit to attempt to
source very large currents. In this case, the LTC4257 will
quickly go into thermal shutdown.
Power Good Interface
The PWRGD signal is controlled by a high voltage, open-
drain transistor. Examples of active-high and active-low
interface circuits for controlling the PD load are shown in
Figure 10.
In some applications it is desirable to ignore intermittent
power bad conditions. This can be accomplished by
including capacitor C15 in Figure 10 to form a lowpass
filter. With the components shown, power bad conditions
less than about 200µs will be ignored. Conversely, in other
applications it may be desirable to delay assertion of
PWRGD to the PD load. The PWRGD signal can be delayed
with the addition of capacitor C17 in Figure 10.
CLASS
FMMT2222
pin should not be shorted to V
C15*
0.047µF
10V
C15*
0.047µF
10V
INTERNAL
PULLUP
Q1
SHDN
LOAD
PD
C17*
RUN
LOAD
PD
4257 F10
LTC4257
IN
as this would
15
4257fb