L6743Q STMicroelectronics, L6743Q Datasheet - Page 8

• Manufacturer Part Number: L6743Q
• Description: IC MOSFET DRIVER HI CURR 10-DFN
• Manufacturer: STMicroelectronics
• Type: High Side/Low Sider

Specifications of L6743Q

• Configuration: High and Low Side, Synchronous
• Input Type: Non-Inverting
• Current - Peak: 2A
• Number Of Configurations: 1
• Number Of Outputs: 2
• Voltage - Supply: 5 V ~ 12 V
• Operating Temperature: 0°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-DFN
• Supply Voltage (min): 5 V
• Supply Current: 5 mA
• Maximum Power Dissipation: 2250 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Number Of Drivers: 2
• Flexible Gate-drive: 5V to 12V compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time: -
• High Side Voltage - Max (bootstrap): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Device description and operation
5.1
5.2
8/17
High-impedance (HiZ) management
The driver is able to manage high-impedance state by keeping all MOSFETs in off state in
two different ways.
●
●
The implementation of the high-impedance state allows the controller that will be connected
to the driver to manage high-impedance state of its output, avoiding to produce negative
undershoot on the regulated voltage during the shut-down stage. Furthermore, different
power management states may be managed such as pre-bias start-up.
Preliminary OV protection
After VCC has overcome its UVLO threshold and while in HiZ, L6743, L6743Q activates the
Preliminary-OV protection.
The intent of this protection is to protect the load especially from high-side MOSFET failures
during the system start-up. In fact, VRM, and more in general PWM controllers, have a 12 V
bus compatible turn-on threshold and results to be non-operative if VCC is below that turn-
on thresholds (that results being in the range of about 10 V). In case of a high-side MOSFET
failure, the controller won’t recognize the over voltage until VCC = ~10 V (unless other
special features are implemented): but in that case the output voltage is already at the same
voltage (~10 V) and the load (CPU in most cases) already burnt.
L6743, L6743Q by-pass the PWM controller by latching on the low-side MOSFET in case
the PHASE pin voltage overcome
the HiZ window, the protection is reset and the control of the output voltage is transferred to
the controller connected to the PWM input.
Since the driver has its own UVLO threshold, a simple way to provide protection to the
output in all conditions when the device is OFF consists in supplying the controller through
the 5 V
short, the low-side MOSFET is driven with 5 V assuring a reliable protection of the load.
Preliminary OV is active after UVLO and while the driver is in HiZ state and it is disabled
after the first PWM transition. The controller will have to manage its output voltage from that
time on.
If the EN signal is pulled low, the device will keep all MOSFETs OFF careless of the
PWM status.
When EN is asserted, if the PWM signal remains in the HiZ window for a time longer
than the hold-off time, the device detects the HiZ condition so turning off all the
MOSFETs. The HiZ window is defined as the PWM voltage range comprised between
V
The device exits from the HiZ state only after a PWM transition to logic zero (V
V
See
PWM_IL
PWM_IL
SB
Figure 4
bus: 5 V
).
and V
for details about HiZ timings.
SB
PWM_IH
is always present before any other voltage and, in case of High-Side
.
2 V
during the HiZ state. When the PWM input exits form
L6743, L6743Q
PWM
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