L6388ED STMicroelectronics, L6388ED Datasheet
L6388ED
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L6388ED Summary of contents
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Features ■ High voltage rail up to 600V ■ dV/dt immunity ±50V/nsec in full temperature range ■ Driver current capability: – 400mA source, – 650mA sink ■ Switching times 70/40 nsec rise/fall with 1nF load ■ 3.3V, 5V, 15V CMOS/TTL ...
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Contents Contents 1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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L6388E 1 Electrical data 1.1 Absolute maximum ratings Table 1. Absolute maximum ratings Symbol V Output voltage out V Supply voltage cc V Floating supply voltage boot V High side gate output voltage hvg V Low side gate output voltage ...
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Pin connection 2 Pin connection Figure 2. Pin connection (Top view) Table 4. Pin description N° Pin 1 LIN 2 HIN GND (1) 5 LVG 6 VOUT (1) 7 HVG 8 V boot 1. The circuit ...
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L6388E 3 Electrical characteristics 3.1 AC operation Table 5. AC operation electrical characteristcs (V Symbol Pin off 3.2 DC operation ...
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Electrical characteristics Table 6. DC operation electrical characteristcs (continued)(V Symbol Pin High/low side driver I Source short circuit current so 5,7 I Sink short circuit current si Logic inputs V Low level logic input voltage il V High level logic ...
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L6388E 4 Waveforms definitions Figure 3. Dead time waveforms definitions LIN H IN LVG HVG Figure 4. Propagation delay waveform definitions Waveforms definitions 7/18 ...
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Input logic 5 Input logic Input logic is provided with an interlocking circuitry which avoids the two outputs (LVG, HVG active at the same time when both the logic input pins (LIN, HIN) are at a high logic ...
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L6388E The following equation is useful to compute the drop on the bootstrap DMOS: where Q is the gate charge of the external power MOS, R gate bootstrap DMOS, and T For example: using a power MOS with a total ...
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Bootstrap driver Figure 5. Bootstrap driver 10/18 D BOOT V BOOT HVG V OUT LVG a V BOOT HVG V OUT LVG b L6388E H.V. C BOOT TO LOAD H.V. C BOOT TO LOAD ...
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L6388E 7 Typical characteristic Figure 6. Typical rise and fall times vs load capacitance time (nsec) 250 200 150 100 For both high and low side buffers @25˚C Tamb Figure 8. V BOOT vs temperature 13 ...
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Typical characteristic Figure 12 temperature Typ -45 -25 12/18 UV turn on threshold vs Figure 13. Output sink current 100 125 Tj (˚C) temperature 1000 @ ...
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L6388E 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on ...
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Package mechanical data Figure 14. DIP-8 mechanical data and package dimensions mm DIM. MIN. TYP. A 3.32 a1 0.51 B 1.15 b 0.356 b1 0.204 D E 7.95 e 2.54 e3 7. 3.18 Z 14/18 ...
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L6388E Figure 15. SO-8 mechanical data and package dimensions mm DIM. MIN. TYP 0.100 A2 1.250 b 0.280 c 0.170 (1) 4.800 4.900 D E 5.800 6.000 (2) 3.800 3.900 E1 e 1.270 h 0.250 L 0.400 L1 ...
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... Order codes 9 Order codes Table 7. Order codes Part number L6388E L6388ED L6388ED013TR 16/18 Package DIP-8 SO-8 SO-8 Tape and reel L6388E Packaging Tube Tube ...
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L6388E 10 Revision history Table 8. Document revision history Date 11-Oct-2007 Revision 1 First release Revision history Changes 17/18 ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...