ISO1H801G Infineon Technologies, ISO1H801G Datasheet - Page 7

• Manufacturer Part Number: ISO1H801G
• Description: IC SWITCH HISIDE 8CH DSO-36
• Manufacturer: Infineon Technologies
• Series: ISOFACE™r
• Type: High Sider

Specifications of ISO1H801G

• Input Type: Parallel
• Number Of Outputs: 8
• On-state Resistance: 150 mOhm
• Current - Output / Channel: 700mA
• Current - Peak Output: 1.4A
• Voltage - Supply: 15 V ~ 30 V
• Operating Temperature: -25°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: DSO-36
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SP000260029

3
3.1
The ISOFACE ISO1H801G includes 8 high-side power
switches that are controlled by means of the integrated
parallel interface. The interface is 8bit µC compatible.
Furthermore a direct control mode can be selected that
allows the direct control of the outputs OUT0...OUT7 by
means of the inputs D0...D7 without any additional logic
signal. The IC can replace 8 optocouplers and the 8
high-side switches in conventional I/O-Applications as
a galvanic isolation is implemented by means of the
integrated coreless transformer technology. The µC
compatible interfaces allow a direct connection to the
ports of a microcontroller without the need for other
components. Each of the 8 high-side power switches is
protected
overtemperature and against overvoltage by an active
zener clamp.
The diagnostic logic on the power chip recognizes the
overtemperature information of each power transistor.
3.2
The IC contains 2 galvanic isolated voltage domains
that are independent from each other. The input
interface is supplied at VCC and the output stage is
supplied at Vbb. The different voltage domains can be
switched on at different time. The output stage is only
enabled once the input stage enters a stable state.
3.3
Each channel contains a high-side vertical power FET
that is protected by embedded protection functions.
The continous current for each channel is 625mA (all
channels ON).
3.3.1
Each output is independently controlled by an output
latch and a common reset line via the pin DIS that
disables all eight outputs and reset the latches. The
parallel input data is transferred to the input latches
with a high-to-low transition of the signal WR (write)
while the CS is logic low. A low-to-high transition of CS
transfers then the data of the input latches to the output
buffer.
3.3.2
Each of the eight output stages has it own zener clamp
that causes a voltage limitation at the power transistor
Datasheet
Functional Description
Introduction
against
Power Supply
Output Stage
Output Stage Control
Power Transistor Overvoltage
Protection
short
to
Vbb,
overload,
7
when solenoid loads are switched off. V
clamped to 47V (min.).
Figure 3
Energy is stored in the load inductance during an
inductive load switch-off.
Figure 4
While demagnetizing the load inductance, the energy
dissipation in the DMOS is
with an approximate solution for R
3.3.3
The outputs are provided with a current limitation that
enters a repetitive switched mode after an initial peak
current has been exceeded. The initial peak short
circuit current limit is set to I
mode short circuit current the limit is set to I
operation leads to an overtemperature condition, a
second protection level (T
E
E
E
L
AS
AS
=
=
=
1 2 ⁄ L I
E
--------------- -
2 R
I
bb
L
V
×
bb
×
+
×
L
E
L
L
Inductive and overvoltage output
clamp (each channel)
Inductive load switch-off energy
dissipation (each channel)
Power Transistor Overcurrent
Protection
×
×
–
(
L
E
V
Dx
2
R
bb
=
+
V
E
V
ON CL
bb
GNDbb
ON CL
(
GNDbb
Vbb
(
Vz
j
)
L(SCp)
×
)
> 135°C) will change the
OUTx
)
i
Functional Description
Version 2.3, 2009-09-16
L
×
t ( )dt
ln
. During the repetitive
OUTx
L


E
Vbb
1
AS
> 0Ω:
+
Z
------------------------ -
L
V
I
ISOFACE™
ISO1H801G
L
ON CL
R
L
×
L
V
(
R
ON
L(SCr)
ON
E
L
Vbb
Load
E
E
)
L
R


is then
. If this