MCZ33976EG Freescale Semiconductor, MCZ33976EG Datasheet - Page 14

• Manufacturer Part Number: MCZ33976EG
• Description: IC DRIVER DUAL GAUGE SPI 24-SOIC
• Manufacturer: Freescale Semiconductor
• Type: Serial Peripheral Interface (SPI) Dual Step Motor Gauge Driverr

Specifications of MCZ33976EG

• Applications: Stepper Motor Driver, 2 Phase
• Number Of Outputs: 2
• Current - Output: 100mA
• Voltage - Supply: 6.5 V ~ 26 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Supply Current: 4 mA
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Load: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

be clocked out into the SO pin, or (6) send a null command
for the purpose of reading the status bits. This register is also
used to place the 33976 into a low current consumption
mode.
logic [1] to their assigned address bits, PE0 and PE1
respectively. This feature could be used to disable a driver if
it is failing or is not being used. The device can be placed into
a standby current mode by writing a logic [0] to both PE0 and
PE1. During this state, most current consuming circuits are
biased off. When in the Standby mode, the internal clock will
remain ON.
times defining the duration that the motor will spend at each
microstep as it accelerates or decelerates to a commanded
position. The accuracy of the acceleration and velocity of the
motor is directly related to the accuracy of the internal clock.
Although the accuracy of the internal clock is temperature
independent, the non-calibrated tolerance is +70% to -35%.
The 33976 was designed with a feature allowing the internal
clock to be software calibrated to a tighter tolerance of ±10%,
using the
microcontroller.
logic [1] to PE3. The calibration pulse, which must be 8.0 µs
for an internal clock speed of 1.0 MHz, will be sent on the
pin immediately after the SPI word is sent. No other SPI lines
will be toggled. A clock calibration will be allowed only if the
gauges are disabled or the pointers are not moving, as
indicated by status bits MOV0 and MOV1. Additional details
are provided in the
beginning on page 30.
pointer velocity and acceleration. Guaranteeing these
maximums requires that the nominal internal clock frequency
fall below 1.0 MHz. The frequency range of the calibrated
clock will always be below 1.0 MHz if bit PE4 is logic [0] when
initiating a calibration command, followed by an 8.0 µs
reference pulse. The frequency will be centered at 1.0 MHz if
bit PE4 is logic [1].
due to a lower motor gear reduction ratio. Writing a logic [1]
to bit PE2 will slow the internal oscillator by one-third. Slowing
the clock accommodates a longer calibration pulse without
overrunning the internal counter—a condition designed to
Table 7. Power, Enable, Calibration, and Configuration Register (PECCR)
The bits in
14
33976
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Read
Write
Bits
Each of the gauge drivers can be enabled by writing a
The internal state machine utilizes a ROM table of step
Calibration of the internal clock is initiated by writing a
Some applications may require a guaranteed maximum
Some applications may require a slower calibrated clock
PE12 (D12) — Null Command for Status Read
PE12
CS
Table 7
D12
–
pin and a reference time pulse provided by the
are write-only.
PE11
Internal Clock Calibration
D11
–
PE10
D10
–
PE9
D9
–
section,
PE8
D8
–
PE7
D7
CS
–
Address 000
PE6
D6
generate a CAL fault indication. For example, calibration for
a clock frequency of 667 kHz would require a calibration
pulse of 12 µs. Unless the internal oscillator is slowed by
writing PE2 to logic [1], a 12 µs calibration pulse may overrun
the counter and generate a CAL fault indication.
than is provided with the air core motor emulation feature.
Writing logic [1] to bit PE5 will disable the air core emulation
for both gauges and provide an acceleration and deceleration
at the maximum that the velocity position ramp can provide.
If the Hold Counts need to be enabled and disabled
dynamically, then the POSxR commands could also be used.
PECCR writes if the device is being used to drive an MMT
style motor. Similarly, this bit must always be written as a
logic [1] when being used to control Switec style motors.
counter-clockwise position. A logic [1] written to bit PE7 will
change the location of the position 0, for the gauge selected
by bit PE8, to the farthest clockwise position. A change in
position 0 of only one, or both, of the two coils can be
accomplished by using bits PE8 and PE7. Performing an RTZ
will always move the pointer to position 0. Exercise care
when writing to PECCR bits PE8 and PE7 in order to prevent
accidental changes of the position 0 locations.
out of the SO pin. When bit PE11 is at logic [0], the clocked
out bits will provide device status. If a logic [1] is written to bit
PE11, the bits clocked out of the SO pin, depending upon the
state of bits PE10:PE8, provides either:
section beginning on page 21.
of PE11:PE0 is ignored. This is referred to as the null
command and can be used to read device status without
affecting device operation.
–
Some applications may require faster pointer positioning
Bit PE6 must always be written as a logic [0] during all
The default Pointer Position 0 (PE7 = 0) will be the farthest
Bits PE11:PE8 determine the content of the bits clocked
• Accumulator information and detection status during
• Real time pointer position location at the time
• The real time step position of the pointer as described
Additional details are provided in the
If bit PE12 is logic [1] during a PECCR command, the state
• 0 = Disable
• 1 = Enable
the RTZ (PE10 logic [0])
low (PE10 logic [1] and PE9 logic [0]), or
in the velocity
logic [1]).
PE5
D5
–
PE4
D4
–
Table
Analog Integrated Circuit Device Data
30, page
PE3
D3
–
Freescale Semiconductor
28
PE2
D2
–
(PE10, PE9, and PE8
SO Communication
PE1
D1
–
CS
PE0
D0
goes
–