PM6685TR STMicroelectronics, PM6685TR Datasheet

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... Mobile system power supply ■ 3 and -4 Cells Li+ battery-powered devices Table 1. Device summary Order code PM6685 PM6685TR March 2011 Dual step-down main supply controller VFQFPN-32 (5mm x 5mm) Description PM6685 is a dual step-down controller specifically designed to provide extremely high efficiency conversion with loss-less current sensing technique ...

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Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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PM6685 8.4 Undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Block diagram 1 Block diagram Figure 1. Functional block diagram VCC VREF PGOOD LDO3 OUT3 SKIP FSEL BOOT3 HGATE3 PHASE3 CSENSE3 COMP3 LDO5 LGATE3 PGOOD3 SHDN LDO3 SEL EN3 4/48 VIN 5V REFERENCE VREF LINEAR GENERATOR REGULATOR LDO5 ENABLE - ...

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PM6685 2 Pin settings 2.1 Connections Figure 2. Pin connection (top view) Doc ID 11674 Rev 8 Pin settings 5/48 ...

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Pin settings 2.2 Functions Table 2. Pin functions Pin Name Signal ground. Reference for internal logic circuitry. It must be connected to the signal ground 1 SGND1 plan of the power supply. The signal ground plan and the power ground ...

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PM6685 Table 2. Pin functions (continued) Pin Name Device input supply voltage. A bypass filter (4W and 4.7mF) between the battery and this pin is 19 VIN recommended. Current sense input for the 5V section. This pin must be connected ...

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Electrical data 3 Electrical data 3.1 Maximum rating Table 3. Absolute maximum ratings COMPx,FSEL,LDO3_SEL,VREF,SKIP to SGND1,SGND2 ENx,SHDN,PGOOD_LDO3,OUTx,PGOODx,VCC to SGND1,SGND2 LDO3 to SGND1,SGND2 LGATEx to PGND HGATEx and BOOTx, to PHASEx PHASEx to PGND CSENSEx, to PGND CSENSEx to BOOTx_ V5SW, ...

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PM6685 4 Electrical characteristics V = 12V 0°C to 85°C, unless otherwise specified IN A Table 5. Electrical characteristics Symbol Parameter Supply section VIN Input voltage range Vcc IC supply voltage Turn-on voltage threshold V Turn-off voltage V5SW ...

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Electrical characteristics Table 5. Electrical characteristics (continued) Symbol Parameter I Input bias current limit CSENSE Comparator offset Zero crossing comparator offset Fixed negative current limit threshold On time pulse width Ton ON-time duration OFF time T Minimum off time OFFMIN ...

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PM6685 Table 5. Electrical characteristics (continued) Symbol Parameter LDO3 linear regulator LDO3 linear output V LDO3 voltage I LDO3 current limit LDO3 High and low gate drivers HGATE Driver On- resistance LGATE Driver On- resistance PGOOD pins UVP/OVP protections OVP ...

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Electrical characteristics Table 5. Electrical characteristics (continued) Symbol Parameter Frequency selection FSEL range LDO3 3.3V linear regulator selection pin SEL Pulse skip mode SKIP PWM mode Frequency clamp mode Input leakage current 1. by demonstration board test 2. by design ...

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PM6685 5 Typical operating characteristics FSEL = GND (200/300 kHz), SKIP = GND (skip mode), LDO3_SEL = VREF, V5SW = OUT5, input voltage VIN = 12 V, SHDN, EN3 and EN5 high, no load unless specified. Figure ...

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Typical operating characteristics Figure 7. Standby mode input battery current vs input voltage Figure 9. 5V switching frequency vs load current Figure 11. LDO5 vs output voltage 14/48 Figure 8. Shutdown mode input device current vs input voltage Figure 10. ...

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PM6685 Figure 13. 5V voltage regulation vs load current Figure 15. Voltage reference vs load current Figure 17 PWM load transient Typical operating characteristics Figure 14. 3.3 V voltage regulation vs load current Figure 16. OUT5, LDO3 and ...

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Typical operating characteristics Figure 19 soft start (0.75 Figure 21 soft end (no load) Ω Figure 23 soft end (1 16/48 Ω load) Figure 20. 3.3 V soft start (0.55 Figure 22. 3.3 V ...

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PM6685 Figure 25 audible skip mode Typical operating characteristics Figure 26. 3 audible skip mode Doc ID 11674 Rev 8 17/48 ...

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Application schematic 6 Application schematic Figure 27. Simplified application schematic 18/48 4 EN3 25 EN5 32 VREF 24 SKIP 3 FSEL Doc ID 11674 Rev 8 PM6685 31 VCC 18 LDO5 19 VIN ...

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PM6685 7 Device description The PM6685 is a dual step-down controller dedicated to provide logic voltages for notebook computers based on a Constant On Time control architecture. This type of control offers a very fast load transient response ...

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Device description Figure 28. Constant on time PWM control The duty cycle D of the buck converter in steady state is: Equation 2 The PWM control works at a nearly fixed frequency f Equation 3 As mentioned the steady state ...

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PM6685 7.2 Constant on time architecture Figure 29 on page 21 minimum off-time constrain (380 ns typ) is introduced to allow inductor valley current sensing on the synchronous switch. A minimum on-time(150 ns typ) is also introduced to assure the ...

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Device description Figure 30. Circuitry for output ripple compensation COMP PIN COMP PIN VOL TA GE VOL TPU T VOLTAGE OU TPU T VOLTAGE The integrator amplifier generates a current, proportional to the DC errors, ...

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PM6685 Figure 31. PWM and pulse skip mode inductor current 7.5 No-audible skip mode If SKIP pin is tied to V kHz is enabled. At light load condition, If there is not a new switching cycle within a 30 µs ...

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Device description Figure 33. R DSON An internal 100 μA ΔI a voltage drop on R voltage drop, the controller doesn’t initiate a new cycle. A new cycle starts only when the sensed current goes below the current limit. Since ...

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PM6685 The valley current limit can be set with resistor R Equation 6 Where I = 100 µA, R CSENSE Consider the temperature effect and the worst case value in R The accuracy of the valley current threshold detection depends ...

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Device description Figure 35. Soft start waveforms When a switching section is turned off(EN5/EN3 pins low), the controller enters in soft end mode. The output capacitor is discharged through an internal 16 Ω P-MOSFET switch; when the output voltage reaches ...

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PM6685 7.9 Reference voltage and bandgap The 1.230 V (typ.) internal bandgap voltage is accurate to ±1% over the temperature range externally available (VREF pin) and can supply up to ±100μA and can be used as a voltage ...

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Device description regulator is turned off and LDO3 output is connected directly to OUT3 pin through an internal 3 Ω max p-channel MOSFET switch. ● If LDO3_SEL is connected to 5V, the internal 3.3 V regulator is always on and ...

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PM6685 8 Monitoring and protections 8.1 Power good signals The PM6685 provides three independent power good signals: one for each switching section(PGOOD5/PGOOD3) and the other for the internal linear regulator LDO3(PGOOD_LDO3). PGOOD5/PGOOD3 signals are low if the output voltage is ...

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Monitoring and protections Table 10. Protections and operatives modes Mode Overvoltage OUT5/OUT3 > 115% of the protection nominal value Undervoltage OUT5/OUT3 < 70% of the protection nominal value Thermal T J shutdown 8.5 Design guidelines The design of a switching ...

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PM6685 where fsw is the switching frequency, VIN is the input voltage, VOUT is the output voltage and ΔIL is the selected inductor ripple current. In order to prevent overtemperature working conditions, inductor must be able to provide an RMS ...

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Monitoring and protections A low ESR capacitor is required to reduce the output voltage ripple. Switching sections can work correctly even with 20 mV output ripple. However, to reduce jitter noise between the two switching sections it’s preferable to work ...

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PM6685 8.10 Power MOSFETs Logic-level MOSFETs are recommended, since low side and high side gate drivers are powered by LDO5. Their breakdown voltage VBR In notebook applications, power management efficiency is a high level requirement. The power dissipation on the ...

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Monitoring and protections Equation 20 Choose a synchronous rectifier with low R variation of the phase node voltage can bring up even the low side gate through its gate- drain capacitance CRSS, causing cross-conduction problems. Choose a low side MOSFET ...

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PM6685 Figure 36. Circuitry for output ripple compensation The stability of the system depends firstly on the output capacitor zero frequency. The following condition should be satisfied: Equation 21 where design parameter greater than 3 and Rout ...

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Monitoring and protections Equation 24 Due to the capacitive divider (CINT, Cfilt), the ripple voltage at the COMP pin is given by: Equation 25 Where VRIPPLEout is the output ripple and q is the attenuation factor of the output ripple. ...

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PM6685 where ΔIL is the inductor current ripple and VRIPPLE is the overall ripple of the T node voltage. It should be chosen higher than approximately 30mV. The stability of the system depends firstly on the output capacitor value and ...

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Monitoring and protections Equation 33 Example: =200 kHz, L=4.7 µH, Cout=100 µF ceramic (Rout~0 Ω). We design 5 V section RESR = 30 mΩ. We choose CINT equations 31, 32 and Cfilt=47 pF, RINT=1.8 kΩ by ...

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PM6685 9 Other parts design ● VIN filter A VIN pin low pass filter is suggested to reduce switching noise. The low pass filter is shown in the next figure: Figure 38. VIN pin filter Typical components values are: R=3.9 ...

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Other parts design Figure 40. Bootstrap circuit The bootstrap circuit capacitor value CBOOT must provide the total gate charge to the high side MOSFET during turn on phase. A typical value is 100 nF. The bootstrap diode D must charge ...

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PM6685 10 Design example The following design example considers an input voltage from The two switching outputs must deliver a maximum current of 5A. The selected switching frequencies are 200 kHz for the 5 V ...

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Design example Low side: STS12NH3LL 10.4 Current limit OUT5: Equation 36 Equation 37 (Let’s assume the maximum temperature Tmax = 75° OUT3: Equation 38 Equation 39 (Let’s assume Tmax = 75° 10.5 Input capacitor Maximum input ...

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PM6685 OUT3: The ripple is greater than 30 mV, then the virtual ESR network is not required nF pF; R INT filt 10.8 Layout guidelines The layout is very important in terms of efficiency, stability ...

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Design example Figure 41. Current paths, ground connection and driver traces layout ● As general rule, make the high side and low side drivers traces wide and short. The high side driver is powered by the bootstrap circuit. It’s very ...

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PM6685 11 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ...

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Package mechanical data Figure 42. VFQFPN 5x5x1.0 32L pitch 0.50 package drawings 46/48 Doc ID 11674 Rev 8 PM6685 ...

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PM6685 12 Revision history * Table 20. Document revision history Date 17-Jan-2006 21-Apr-2006 03-May-2006 29-Jun-2006 11-Sep-2006 24-Oct-2006 18-Oct-2007 30-Mar-2011 Revision 1 Initial release 2 Few updates 3 Graphical updates 4 Mechanical data updated Changes electrical characteristics, added COMP value skip ...

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