LTC1143LCS-ADJ#PBF Linear Technology, LTC1143LCS-ADJ#PBF Datasheet - Page 15

• Manufacturer Part Number: LTC1143LCS-ADJ#PBF
• Description: IC SW REG STEP-DOWN DUAL 16-SOIC
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC1143LCS-ADJ#PBF

• Internal Switch(s): No
• Synchronous Rectifier: No
• Number Of Outputs: 2
• Voltage - Output: Adjustable
• Current - Output: 50mA
• Frequency - Switching: 400kHz
• Voltage - Input: 3.5 ~ 16 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

APPLICATIONS
Auxiliary Windings––Suppressing Burst Mode
Operation
The LTC1143 series operates nonsynchronously with the
normal limitation that the power drawn from the inductor
primary winding must not be less than twice the power
drawn from the auxiliary windings. (With synchronous
switching, using the LTC1142 series, auxiliary outputs
may be loaded without regard to the primary output load,
providing that the loop remains in continuous mode
operation.)
Burst Mode operation can be suppressed at low output
currents with a simple external network that cancels the
25mV minimum current comparator threshold. This tech-
nique is also useful for eliminating audible noise from
certain types of inductors in high current (I
applications when they are lightly loaded.
An external offset is put in series with the Sense
subtract from the built-in 25mV offset. An example of this
technique is shown in Figure 8. Two 100 resistors are
inserted in series with the sense leads from the sense
resistor.
[PIN 16 (8)]
[PIN 1(9)]
Figure 8. Suppression of Burst Mode Operation
SENSE
SENSE
+
–
(a) CONTINUOUS MODE OPERATION
Figure 7. C
U
R3
(b) Burst Mode OPERATION
1000pF
INFORMATION
U
T
100
100
Waveforms
R2
R1
W
+
R
1143 F08
SENSE
C
OUT
U
OUT
V
OUT
–
> 5A)
pin to
LTC1143 • F07
3.3V
0V
3.3V
0V
With the addition of R3 a current is generated though R1,
causing an offset of:
If V
Burst Mode operation is prevented from occurring. Since
V
decreased by the same offset. Thus, to get back to the
same I
To prevent noise spikes from erroneously tripping the
current comparator, a 1000pF capacitor is needed across
Pins 1 (16) and 9 (8).
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1143 series. These items are also illustrated graphi-
cally in the layout diagram of Figure 9. In general, each
block should be self-contained with little cross coupling
for best performance. Check the following in your layout:
1) Are the signal and power grounds segregated? The
2) Does the LTC1143 series SENSE
3) Are the SENSE
4) Does the (+) plate of C
OFFSET
R
V
OFFSET
LTC1143 series GND Pin 3 (11) must return separately
to: a) the power and b) the signal grounds. The
power ground returns to the anode of the Schottky
diode and (–) plate of C
lead lengths as possible.The signal ground (b) con-
nects to the (–) plate of C
to a point close to R
with minimum PC trace spacing? The 1000pF
capacitor between Pins 1 (9) and 16 (8) should be as
close as possible to the LTC1143 series.
P-channel MOSFET as closely as possible? This
capacitor provides the AC current to the P-channel
MOSFET.
OFFSET
SENSE
MAX
is constant, the maximum load current is also
> 25mV, the built-in offset will be cancelled and
, the value of the sense resistor must be lower:
75
V
I
MAX
OUT
mV
–
and SENSE
R
LTC1143/LTC1143L
1
R
SENSE
1
R
IN
IN
3
, which should have as short
connect to the source of the
OUT
and the (+) plate of C
LTC1143L-ADJ
.
+
leads routed together
–
Pin 16 (8) connect
15
OUT
?