L6722 STMicroelectronics, L6722 Datasheet

IC BUCK ADJ 2A TRPL 36VFQFPN

L6722

Manufacturer Part Number
L6722
Description
IC BUCK ADJ 2A TRPL 36VFQFPN
Manufacturer
STMicroelectronics
Type
Step-Down (Buck)r
Datasheet

Specifications of L6722

Internal Switch(s)
No
Synchronous Rectifier
No
Number Of Outputs
3
Voltage - Output
Adj to 0.8V
Current - Output
2A
Frequency - Switching
100kHz
Voltage - Input
12V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
36-VFQFN, 36-VFQFPN
Power - Output
3.5W
Output Voltage
0.8 V to 1.85 V
Output Current
95 A
Input Voltage
13.8 V
Mounting Style
SMD/SMT
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
L6722
Manufacturer:
CHINA
Quantity:
1 979
Part Number:
L6722
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
L6722TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
L6722TR
Manufacturer:
ST
0
Features
Applications
Order codes
May 2006
2A integrated gate drivers
0.8V reference
1% output voltage accuracy
Adjustable reference offset
Precise current sharing and OCP across LS
MOSFETS
Constant over current protection
Feedback disconnection
LSLESS allows managing pre-bias startup
Preliminary of protection
Oscillator internally fixed at 100kHz, externally
adjustable
Power good
Integrated remote sense buffer
VFQFPN36 package with exposed pad
Memory supply for server and workstation MBs
High density DC / DC converters
High current pol
Part number
L6722
L6722
TR
3 Phase controller for DC/DC converters
VFQFPN36
VFQFPN36
Package
Rev 1
Description
L6722 implements a three-phase step-down
controller with 120º phase-shift between each
phase with integrated high-current drivers in a
compact VFQFPN36 package with exposed pad.
L6722 manages output voltages down to 0.8V
with ±1% output voltage accuracy over line and
temperature variations. Additional programmable
offset can be added to the reference voltage with
a single external resistor in order to perform
margining tests.
The controller assures fast protection against load
over current and over / under voltage. In case of
over-current the system works in Constant
Current mode until UVP. Preliminary OVP allows
full load protection in case of startup with failed
HS. Feedback-disconnection protection prevents
from damaging the load in case of misconnections
in the remote sense. Pre-bias start-up is also
managed thanks to LSLESS.
Combined use of DCR and RdsON current
sensing assures precision in voltage positioning
(by reading droop current across inductors DCR)
and safe current sharing and OCP per each
phase (by reading the current across LS RdsON).
Droop function can be anyway disabled to
perform precise and load-insensitive regulation.
VFQFPN36
Tape & Reel
Packing
Tube
L6722
www.st.com
1/34
34

Related parts for L6722

L6722 Summary of contents

Page 1

... VFQFPN36 package with exposed pad. L6722 manages output voltages down to 0.8V with ±1% output voltage accuracy over line and temperature variations. Additional programmable offset can be added to the reference voltage with a single external resistor in order to perform margining tests ...

Page 2

... Droop function (optional 7.3 Maximum duty cycle limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1 Low-side-less startup for pre-bias output . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9 Output voltage monitor and protections . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.1 Under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.2 Over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.3 Preliminary over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.4 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.5 PGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/34 L6722 ...

Page 3

... L6722 9.6 Over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 11 System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 11.1 Compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 12 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 12.1 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 12.2 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . 30 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3/34 ...

Page 4

... Typical application circuit GND VCC IN 4 PGND 1, 26 SGND R 18 OSC OSC/INH/FLT 19 REF_IN 20 REF_OUT 36 COMP VSEN 27 FBR 28 FBG L6722 REFERENCE SCHEMATIC 4/ BOOT1 8 UGATE1 HS1 9 PHASE1 3 LGATE1 LS1 31 R ISEN ISEN1 10 BOOT2 11 UGATE2 HS2 12 PHASE2 5 LGATE2 LS2 30 R ISEN ISEN2 13 BOOT3 14 UGATE3 ...

Page 5

... VCC IN 4 PGND 1, 26 SGND R 18 OSC OSC/INH/FLT 19 REF_IN 20 REF_OUT 36 COMP VSEN 27 FBR 28 FBG L6722 REFERENCE SCHEMATIC - droop 1 Typical application circuit and block diagram BOOT1 8 UGATE1 HS1 9 PHASE1 3 LGATE1 LS1 31 R ISEN ISEN1 10 BOOT2 11 UGATE2 HS2 12 PHASE2 5 LGATE2 LS2 30 R ISEN ...

Page 6

... PGND VCC PGND HS3 LS3 LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION CURRENT SHARING CORRECTION PWM3 OCP1 LOW SIDE MOSFET OCP2 CURRENT READING OCP3 AND OVER CURRENT OVP V FB-DISC SSEND / PGOOD 64k 64k REMOTE 64k BUFFER 64k L6722 ISEN1 ISEN2 ISEN3 PGOOD ...

Page 7

... L6722 2 Pins description and connection diagrams Figure 4. Pins connection (top view) VSEN COMP SGND VCC N.C. LGATE1 PGND LGATE2 2.1 Pin description Table 1. Pins description Pin# Name 1 VSEN COMP 4 SGND 5 VCC 6 N.C. 7 LGATE1 8 PGND Remote Buffer Output. It manages OVP and UVP protections and PGOOD ...

Page 8

... It must be connected to the HS3 mosfet source and provides return path for the HS driver of channel 3. Not Internally Bonded. Open Drain Output set free after SS has finished and pulled low when VSEN is lower than the relative threshold. Pull voltage lower than 5V (typ), if not used it can be left floating. Not Internally Bonded. L6722 ...

Page 9

... L6722 Table 1. Pins description (continued) Pin# Name OSC / INH / 23 FLT 24 N.C. 25 REF_IN 26 REF_OUT 27, 28 N.C. 29 SGND 30 FBR 31 FBG ISEN3 ISEN1 35 CS+ 36 CS- THERMAL PAD PAD 2 Pins description and connection diagrams Function Three functional pin: OSC: It allows programming the switching frequency F channel: the equivalent switching frequency at the load side results in being tripled ...

Page 10

... Thermal Resistance Junction to Ambient R thJA (Device soldered on 2s2p PC Board) T Maximum Junction Temperature MAX T Storage Temperature Range STG T Junction Temperature Range J P Maximum Power Dissipation at T TOT 10/34 Parameter = 25°C A L6722 Value Unit 30 °C/W 150 °C -40 to 150 °C -40 to 125 °C 3.5 W ...

Page 11

... L6722 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol V to PGND Boot Voltage BOOTx PHASEx UGATEx PHASEx LGATEx, PHASEx, to PGNDx All other Pins to PGNDx Positive Peak Voltage; T<20ns @ 600kHz V PHASEx Negative Peak Voltage 3.2 Electrical characteristics Table 4. Electrical characteristics (V = 12V± ...

Page 12

... Rising, above VSEN CS- VSEN Falling, vs. REF_IN VSEN Falling, vs. REF_IN I = -4mA Min. Typ. Max OUT 1.5 2.5 20 1.5 1.8 1.085 1.120 1.155 1.25 300 1.375 -250 -300 -350 -100 -150 -200 0.4 L6722 Unit % dB V/µs V/V dB µA µA µ Ω Ω ...

Page 13

... In addition, droop function may be enabled to perform precise voltage positioning according to the delivered current performed by increasing the reference in 2048 clock cycles in closed loop regulation. L6722 provides a complete set of protections to avoid damaging the load in any operative and non-operative conditions: ● ...

Page 14

... Power dissipation L6722 embeds high current mosfet drivers for both high side and low side mosfets then important to consider the power that the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. In addition, since the device ...

Page 15

... L6722 ● Drivers' power is the power needed by the driver to continuously switch on and off the external mosfets function of the switching frequency and total gate charge of the selected mosfets. It can be quantified considering that the total power P switch the mosfets (easy calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic mosfet resistance and intrinsic driver resistance ...

Page 16

... Current sharing loop and current reading 6 Current sharing loop and current reading L6722 embeds two separate Current-Reading circuitries used to perform Current-Sharing and OCP through ISENx pins and Voltage-Positioning through CS+ and CS- pins (See Current-sharing control-loop and connections are reported in the I pins is converted into a current I ...

Page 17

... Both DROOP and OFFSET function can be disabled: see details. L6722 embeds a Remote Sense Buffer to sense remotely the regulated voltage without any additional external components. In this way, the output voltage programmed is regulated between the remote buffer inputs compensating for board and connector losses. The device ...

Page 18

... DROOP FB 64k 64k COMP VSEN FBR Vout (Remote Sense) ⋅ R OS1 R OS2 ⋅ ) ⋅ ----------------------------------- - OS1 OS1 OS2 V TARGET POS – ⋅ --------------------------------------------------------------------------------------- - OS1 V V – TARGET POS TARGET NEG – filter across CS+ and CS- pins proportional to the average CS L6722 FBG – ...

Page 19

... L6722 Time constant matching between the inductor (L / DCR) and the current reading filter ⋅ required to implement a real equivalent output impedance of the system avoiding over and/or under shoot of the output voltage as a consequence of a load transient. In fact, considering the scheme reported on By applying the time constant matching concept, it results: ...

Page 20

... UVP is detected or anyway until I V OUT 0. 0. Output Char OUT OCP OCPx (I = 35µA) ISENx I 0µA = ISENx I = 35µA ISENx = 35µA. ISENx Limited T ON Limted-T Output Char. ON Desired output Char. Resulting Output Char. UVP Threshold OCP OCPx (I = 35µA) ISENx L6722 I OUT ...

Page 21

... Low-side-less startup for pre-bias output To manage pre-biased output start-up and in order to avoid any kind of negative undershoot and dangerous return from the load, L6722 performs a special sequence in enabling LS driver to switch: during the soft-start phase, the LS driver results disabled (LS=OFF) until the HS starts to switch. This avoid the dangerous negative spike on the output voltage that can happen ...

Page 22

... Output voltage monitor and protections 9 Output voltage monitor and protections L6722 monitors through pin VSEN the regulated voltage and compares this voltage with the one present at the REF_IN pin to manage the OVP, UVP and PGOOD conditions. Protections are active also during soft-start (See 9 ...

Page 23

... Remotely, through the remote buffer, across VSEN ● Locally across the CS- pin (negligibly offset by By comparing the voltage present at these two different locations, L6722 is able to understand if the output voltage feedback is connected. When CS- is more than 1.375V higher than VSEN, (See Figure 13) the device stops switching with the low side mosfets permanently ON and drives high the FAULT pin ...

Page 24

... The high side mosfet can be then turned ON with bottom. The worst-case condition is when OCPx ) is greater than I PEAK resistors safe ISENx of the threshold as follow dsON max ) must be OCPx as follow since the OUT(OCP) ∆ – ----------- - 2 but it can be determined OCPx L6722 ISENx ...

Page 25

... L6722 V ------------------------------------------ - = I + PEAK OCPx Where V is the UVP threshold, (inductor saturation must be considered). When that outMIN threshold is crossed, all mosfets are turned off, the FAULT pin is driven high and the device stops working. Cycle the power supply or the INH pin to restart operation. ...

Page 26

... SGND the frequency is increased according to the following OSC 1.240V ⋅ --------------------------- - F 100kHz = + ( ) SW R kΩ OSC 150 200 250 300 350 Fsw [kHz] Programmed ) connected OSC 6 ⋅ kHz 4.96 10 ---------- - 4 100kHz = + --------------------------- - µ kΩ OSC 400 450 500 550 L6722 ...

Page 27

... L6722 11 System control loop compensation The control loop is composed by the Current Sharing control loop (See Voltage control loop. Each loop gives, with a proper gain, the correction to the PWM in order to minimize the error in its regulation: the Current Sharing control loop equalize the currents in the inductors while the Voltage control loop fixes the output voltage equal to the reference ...

Page 28

... C ESR + ⋅ (s), the transfer function has one (s) LOOP [dB] F ω ω ω ESR ( correspondence with the L-C F =ω and imposing the cross-over F LC might be not higher than 1/10th T L ⋅ ---------------------- - F ESR + R F L6722 R L ------- 3 ω ω T ...

Page 29

... L6722 to move ω ● Increase C F phase margin. Having the fastest compensation network gives not the confidence to satisfy the requirements of the load: the inductor still limits the maximum dI/dt that the system can afford. In fact, when a load transient is applied, the best that the controller can “saturate” the duty cycle to its maximum ( minimum (0) value ...

Page 30

... Two kind of critical components and connections have to be considered when layouting a VR based on L6722: power components and connections and small signal components connections. 12.1 Power components and connections These are the components and connections where switching and high continuous current flows from the input to the load ...

Page 31

... L6722 Remote Sense Connection must be routed as parallel nets from the FBG/FBR pins to the load in order to avoid the pick-up of any common mode noise. Connecting these pins in points far from the load will cause a non-optimum load regulation, increasing output tolerance. Locate current reading components close to the device. It's also important to minimize any offset in the measurement and, to get a better precision, to connect the traces as close as possible to the sensing elements ...

Page 32

... VFQFPN-36 (6x6x1.0mm) 0.014 0.022 0.029 Very Fine Quad Flat Package No lead 0.003 OUTLINE AND MECHANICAL DATA 7185332 F L6722 ...

Page 33

... L6722 13 Revision history Table 5. Revision history Date Revision 14-Apr-2006 1 Initial release. 13 Revision history Changes 33/34 ...

Page 34

... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 34/34 Please Read Carefully: © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com L6722 ...

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