MT18VDDF12872Y-40BF1 Micron Technology Inc, MT18VDDF12872Y-40BF1 Datasheet - Page 27

• Manufacturer Part Number: MT18VDDF12872Y-40BF1
• Description: MODULE DDR SDRAM 1GB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDF12872Y-40BF1

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 1.8A
• Number Of Elements: 18
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1233; MT18VDDF12872Y-40BF1

Table 19: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
Table 20: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
NOTE:
pdf: 09005aef80f6b913, source: 09005aef80f6b41c
DDAF18C64_128x72G.fm - Rev. C 9/04 EN
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
PARAMETER/CONDITION
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: I
INPUT LEAKAGE CURRENT: V
OUTPUT LEAKAGE CURRENT: V
STANDBY CURRENT:
SCL = SDA = V
POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
edge of SDA.
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
DD
- 0.3V; All other inputs = GND or 3.3V ±10%
OUT
SS
SS
IN
; V
; V
= 3mA
OUT
= GND to V
DDSPD
DDSPD
= GND to V
= +2.3V to +3.6V
= +2.3V to +3.6V
t
WRC) is the time from a valid stop condition of a write sequence to the end of
DD
DD
27
512MB, 1GB (x72, ECC, SR) PC3200
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SYMBOL
184-PIN DDR SDRAM RDIMM
V
SYMBOL
t
t
t
t
t
HD:DAT
HD:STA
SU:DAT
DDSPD
SU:STA
SU:STO
V
t
V
t
t
I
V
I
I
t
HIGH
I
LOW
f
WRC
LO
CC
t
t
SB
OL
BUF
LI
IH
SCL
AA
DH
IL
t
t
t
F
R
I
V
DD
MIN
MIN
200
100
2.3
0.2
1.3
0.6
0.6
1.3
0.6
0.6
-1
–
–
–
–
–
0
x 0.7
MAX
©2004 Micron Technology, Inc. All rights reserved.
300
400
0.9
0.3
50
10
V
V
DD
DD
MAX
3.6
0.4
10
10
30
2
+ 0.5
x 0.3
UNITS
KHz
ms
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
UNITS
mA
NOTES
µA
µA
µA
V
V
V
V
1
2
2
3
4