MT16VDDT6464AY-335K1 Micron Technology Inc, MT16VDDT6464AY-335K1 Datasheet - Page 7

• Manufacturer Part Number: MT16VDDT6464AY-335K1
• Description: MODULE DDR 512MB 167MHZ 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16VDDT6464AY-335K1

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184UDIMM
• Device Core Size: 64b
• Organization: 64Mx64
• Total Density: 512MByte
• Chip Density: 256Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.432A
• Number Of Elements: 16
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General Description
Serial Presence-Detect Operation
PDF: 09005aef80739fa5/Source:09005aef807397e5
DD16C64_128_256x64A.fm - Rev. E 8/08 EN
The MT16VDDT6464A, MT16VDDT12864A, and MT16VDDT25664A are high-speed,
CMOS dynamic random access 512MB, 1GB, and 2GB memory modules organized in a
x64 configuration. These modules use DDR SDRAM devices with four internal banks.
DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for DDR SDRAM modules effectively consists of a single
2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Control, command, and address signals are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
These DDR SDRAM modules incorporate serial presence-detect. The SPD data is stored
in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the
module type and various DDR SDRAM organizations and timing parameters. The
remaining 128 bytes of storage are available for use by the customer. System READ/
WRITE operations between the master (system logic) and the slave EEPROM device
occur via a standard I
together with SA[2:0], which provide eight unique DIMM/EEPROM addresses. Write
protect (WP) is connected to V
512MB, 1GB, 2GB (x64, DR) 184-Pin DDR SDRAM UDIMM
2
C bus using the DIMM’s SCL (clock) and SDA (data) signals,
7
SS
, permanently disabling hardware write protect.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2004 Micron Technology, Inc. All rights reserved