MT16LSDT3264AG-133G3 Micron Technology Inc, MT16LSDT3264AG-133G3 Datasheet - Page 8

• Manufacturer Part Number: MT16LSDT3264AG-133G3
• Description: MODULE SDRAM 256MB 168-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16LSDT3264AG-133G3

• Memory Type: SDRAM
• Memory Size: 256MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168UDIMM
• Device Core Size: 64b
• Organization: 32Mx64
• Total Density: 256MByte
• Chip Density: 128Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 1.216A
• Number Of Elements: 16
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

General Description
high-speed CMOS, dynamic random-access, 128MB
and 256MB memory modules organized in a x64 con-
figuration. These modules use internally configured
quad-bank SDRAMs with a synchronous interface (all
signals are registered on the positive edge of the clock
signals CK).
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select the device bank, A0–A11
select the device row). The address bits registered
coincident with the READ or WRITE command are
used to select the starting column location for the
burst access.
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An AUTO PRE-
CHARGE function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst sequence.
ture to achieve high-speed operation. This architec-
ture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one device
bank while accessing one of the other three device
banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
low-power memory systems. An auto refresh mode is
provided, along with a power-saving, power-down
mode. All inputs and outputs are LVTTL-compatible.
DRAM operating performance, including the ability to
synchronously burst data at a high data rate with auto-
matic column-address generation, the ability to inter-
leave between internal banks in order to hide
precharge time and the capability to randomly change
column addresses on each clock cycle during a burst
access. For more information regarding SDRAM opera-
tion, refer to the 128Mb SDRAM component data
sheets.
09005aef80bccbe7
SD8_16C16_32x64AG.fm - Rev. E 12/05 EN
The MT8LSDT1664A and MT16LSDT3264A are
Read and write accesses to the SDRAM modules are
The modules provide for programmable READ or
SDRAM modules use an internal pipelined architec-
SDRAM modules are designed to operate in 3.3V,
SDRAM modules offer substantial advances in
8
128MB (x64, SR), 256MB (x64, DR)
Serial Presence-Detect Operation
(SPD). The SPD function is implemented using a
2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard IIC bus
using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses.
Initialization
predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to V
neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100µs delay
prior to issuing any command other than a COM-
MAND INHIBIT or NOP. Starting at some point during
this 100µs period and continuing at least through the
end of this period, Command Inhibit or NOP com-
mands should be applied.
one Command Inhibit or NOP command having been
applied, a PRECHARGE command should be applied.
All device banks must then be precharged, thereby
placing the device in the all banks idle state.
be performed. After the AUTO refresh cycles are com-
plete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an
unknown state, it should be loaded prior to applying
any operational command.
Mode Register Definition
mode of operation of the SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency, an operating mode and a write burst
mode, as shown in the Mode Register Definition Dia-
gram. The mode register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.
SDRAM modules incorporate serial presence-detect
SDRAMs must be powered up and initialized in a
Once the 100µs delay has been satisfied with at least
Once in the idle state, two AUTO refresh cycles must
The mode register is used to define the specific
Micron Technology, Inc., reserves the right to change products or specifications without notice.
168-PIN SDRAM UDIMM
©2003, 2004 Micron Technology, Inc. All rights reserved.
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